وڪيپيڊيا sdwiki https://sd.wikipedia.org/wiki/%D9%85%D9%8F%DA%A9_%D8%B5%D9%81%D8%AD%D9%88 MediaWiki 1.46.0-wmf.24 first-letter ذريعات خاص بحث واپرائيندڙ واپرائيندڙ بحث وڪيپيڊيا وڪيپيڊيا بحث فائل فائل بحث ذريعات وڪي ذريعات وڪي بحث سانچو سانچو بحث مدد مدد بحث زمرو زمرو بحث باب باب بحث TimedText TimedText talk ماڊيول ماڊيول بحث Event Event talk 0 8703 371852 370540 2026-04-17T01:05:57Z CommonsDelinker 103 Replacing 4f3bdb2b3891715176c6580e6ab6cb4b--ottoman-empire-sultan.jpg with [[File:Sultan_Abdulaziz.jpg]] (by [[:c:User:CommonsDelinker|CommonsDelinker]] because: [[:c:COM:FR|File renamed]]: [[:c:COM:FR#FR2|Criterion 2]] (meaningless or ambiguous name)). 371852 wikitext text/x-wiki {{Short description|none}} '''عثماني سلطنت جا سلطان''' ([[ترڪي ٻولي|ترڪي]]: <small>Osmanlı</small> <small>padişahları</small>)، جيڪي سڀئي عثماني خاندان (عثمان جو گھر) جا ميمبر هئا، 1299ع ۾ ان جي تصور ڪيل شروعات کان وٺي 1922 ۾ ان جي خاتمي تائين بين البراعظمي سلطنت تي حڪومت ڪئي. پنهنجي عروج تي، عثماني سلطنت اتر ۾ هنگري کان ڏکڻ ۾ يمن ۽ اولهه ۾ الجيريا کان اوڀر ۾ عراق تائين هڪ علائقو پکڙيل هئي. 1280 کان اڳ کان پهرين سوگٽ شهر کان ۽ پوءِ 1323 يا 1324ع کان بورسا شهر کان انتظامي طور تي، سلطنت جي گاديءَ جو هنڌ مراد اول جي فتح کان پوءِ 1363 ۾ ايڊرينوپل (هاڻي انگريزي ۾ ايڊرين جي نالي سان مشهور آهي) ۽ پوءِ محمد دوم جي فتح کان پوءِ 1453ع ۾ قسطنطنيه (هاڻوڪي استنبول) منتقل ڪيو ويو. عثماني سلطنت جا شروعاتي سال مختلف روايتن جو موضوع رهيا آهن، ڇاڪاڻ ته ڏند ڪٿا مان حقيقت کي سمجهڻ ۾ ڏکيائي ٿي رهي هئي. سلطنت 13 صدي جي آخر ۾ وجود ۾ آئي، ۽ ان جو پهريون حڪمران (۽ سلطنت جو نالو) عثمان اول هو. بعد ۾، اڪثر ڪري ناقابل اعتبار عثماني روايت موجب، عثمان اوغوز ترڪن جي قائي قبيلي جو اولاد هو. هن جيڪو عثماني خاندان قائم ڪيو هو اهو 36 سلطانن جي دور ۾ ڇهن صدين تائين قائم رهيو. عثماني سلطنت مرڪزي طاقتن جي شڪست جي نتيجي ۾ غائب ٿي وئي، جن سان هن پهرين عالمي جنگ دوران اتحاد ڪيو هو. فاتح اتحادين پاران سلطنت جي ورهاڱي ۽ ان کان پوءِ ترڪي جي آزادي جي جنگ 1922 ۾ سلطنت جي خاتمي ۽ 1922 ۾ جديد جمهوريه ترڪي جي پيدائش جو سبب بڻي. {{Infobox settlement | native_name = ''Osmanlı padişahı'' | image = Sultan Mehmed VI of the Ottoman Empire.jpg | caption = '''Last to reign'''<br />'''[[Mehmed VI]]'''<br />4 July 1918 – 1 November 1922 |name=عثماني سلطنت|official_name=Ottoman Empire|native_name_lang=tu|settlement_type=B|other_name=A|type=C|image_size=200px|image_caption=B|image_blank_emblem=Osmanli-nisani.svg|blank_emblem_size=90px|blank_emblem_type=ڪوٽ آف آرمز '''[[Coat of arms of the Ottoman Empire|Imperial coat of arms]]''' (from 1882)|seat=مقرر ڪندڙ: [[Line of succession to the Ottoman throne|Hereditary]] شروعات: {{circa}} 1299 حدود: imperial پهريون سلطان: [[Osman I]] ({{circa}} 1299–1323/4) آخري سلطان: [[Mehmed VI]] (1918–1922) خاتمو: [[Abolition of the Ottoman Sultanate|1 November 1922]] حدود: the Ottoman Empire شاهي لقب: سلطان اسٽائل:[[His Imperial Majesty]] رهائش: [[List of Ottoman palaces in Istanbul|Palaces in Istanbul]]: *[[Eski Saray]] *[[Topkapı Palace|Topkapı]] (1460s–1853) *[[Dolmabahçe Palace|Dolmabahçe]] (1853–1889; 1909–1922) *[[Yıldız Palace|Yıldız]] (1889–1909)}} [[File:Imperial standard of the Ottoman Sultan.svg|thumb|240px|Ottoman Imperial Standard]] [[File:Ottoman sultans family tree (EN) by shakko.jpg|thumb|left|80px|Family tree]] [[File:OttomanEmpire1683.png|thumb|240px|سال 1683ع ۾ [[عثماني سلطنت]]، [[يُورَپ|يورپ]] ۾ پنهنجي علائقائي توسيع جي عروج تي.]] == نالا == == عثماني سلطنت جي رياستي تنظيم == == سلطانن جي فهرست == == پڻ ڏسو == == نوٽ == == حوالا == == ٻاهريان ڳنڍڻا == [[sultan]]s of the [[Ottoman Empire]] ({{langx|tr|Osmanlı padişahları}}), who were all members of the [[Ottoman dynasty]] (House of Osman), ruled over the [[Boundaries between the continents|transcontinental]] empire from its perceived inception in 1299 to [[Dissolution of the Ottoman Empire|its dissolution]] in 1922. At its height, the Ottoman Empire spanned an area from [[Budin Eyalet|Hungary]] in the north to [[Yemen Eyalet|Yemen]] in the south and from [[Ottoman Algeria|Algeria]] in the west to [[Ottoman Iraq|Iraq]] in the east. Administered at first from the city of [[Söğüt]] since before 1280 and then from the city of [[Bursa]] since 1323 or 1324, the empire's capital was moved to Adrianople (now known as [[Edirne]] in English) in 1363 following [[Ottoman conquest of Adrianople|its conquest]] by [[Murad I]] and then to [[Constantinople]] (present-day [[Istanbul]]) in 1453 following [[Fall of Constantinople|its conquest]] by [[Mehmed the Conqueror|Mehmed II]].<ref>[[#Sta01|Stavrides 2001]], p. 21</ref> The [[Rise of the Ottoman Empire|Ottoman Empire's early years]] have been the subject of varying narratives, due to the difficulty of discerning fact from legend. The empire came into existence at the end of the 13th century, and its first ruler (and the namesake of the Empire) was [[Osman I]]. According to later, often unreliable Ottoman tradition, Osman was a descendant of the [[Kayı tribe]] of the [[Oghuz Turks]].<ref>[[#Kaf95|Kafadar 1995]], p. 122. "That they hailed from the Kayı branch of the Oğuz confederacy seems to be a creative "rediscovery" in the genealogical concoction of the fifteenth century. It is missing not only in Ahmedi but also, and more importantly, in the Yahşi Fakih-Aşıkpaşazade narrative, which gives its own version of an elaborate genealogical family tree going back to Noah. If there was a particularly significant claim to Kayı lineage, it is hard to imagine that Yahşi Fakih would not have heard of it."<br/> [[#Low03|Lowry 2003]], p. 78. "Based on these charters, all of which were drawn up between 1324 and 1360 (almost one hundred fifty years prior to the emergence of the Ottoman dynastic myth identifying them as members of the Kayı branch of the Oguz federation of Turkish tribes), we may posit that..."<br/> [[#Lin83|Lindner 1983]], p. 10. "In fact, no matter how one were to try, the sources simply do not allow the recovery of a family tree linking the antecedents of Osman to the Kayı of the Oğuz tribe. Without a proven genealogy, or even without evidence of sufficient care to produce a single genealogy to be presented to all the court chroniclers, there obviously could be no tribe; thus, the tribe was not a factor in early Ottoman history."</ref> The eponymous Ottoman dynasty he founded endured for six centuries through the reigns of 36 sultans. The Ottoman Empire disappeared as a result of the defeat of the [[Central Powers]], with whom it had allied itself during [[World War I]]. The [[Partition of the Ottoman Empire|partitioning of the Empire]] by the victorious [[Allies of World War I|Allies]] and the ensuing [[Turkish War of Independence]] led to the [[Abolition of the Ottoman sultanate|abolition of the sultanate]] in 1922 and the birth of the modern [[Turkey|Republic of Turkey]] in 1922.<ref>[[#Gla96|Glazer 1996]], "War of Independence"</ref> ==Names== The sultan was also referred to as the [[padishah]]<!--From English translation of 1876 constitution--> ({{langx|ota|پادشاه|pâdişâh}}, {{langx|fr|Padichah}}<!--French is important in the late Ottoman, Tanzimat and post Tanzimat history, see [[Languages of the Ottoman Empire]]-->). In Ottoman usage the word "Padishah" was usually used except "sultan" was used when he was directly named.<ref name=Straussp4344>[[#Str10|Strauss 2010]], pp. 21–51.</ref> In several European languages, he was referred to as the ''Grand Turk'', as the ruler of the Turks,<ref>{{Latins in the Levant}}</ref> or simply the "Great Lord" (''il Gran Signore'', ''le grand seigneur'') especially in the 16th century. [[Languages of the Ottoman Empire|Names of the sultan in languages used by ethnic minorities]]:<ref name="Straussp4344" /> * [[Arabic]]: In some documents "padishah" was replaced by "[[malik]]" ("king")<ref name=Straussp4344/> * [[Bulgarian language|Bulgarian]]: In earlier periods Bulgarian people called him the "[[tsar]]". The translation of the [[Ottoman Constitution of 1876]] instead used direct translations of "sultan" (Султан ''Sultan'') and "padishah" (Падишах ''Padišax'')<ref name=Straussp4344/> * [[Greek language|Greek]]: In earlier periods the Greeks used the Byzantine Empire-style name "[[basileus]]". The translation of the Ottoman Constitution of 1876 instead used a direct transliterations of "sultan" (Σουλτάνος ''Soultanos'') and "padishah" (ΠΑΔΙΣΑΧ ''padisach'').<ref name=Straussp4344/> * [[Judaeo-Spanish]]: Especially in older documents, ''El Rey'' ("the king") was used. In addition some Ladino documents used ''sultan'' (in Hebrew characters: שולטן and סולטן).<ref name=Straussp4344/> == State organisation of the Ottoman Empire == {{main article|State organisation of the Ottoman Empire}} The Ottoman Empire was an [[absolute monarchy]] during much of its existence. By the second half of the fifteenth century, the sultan sat at the apex of a hierarchical system and acted in political, military, judicial, social, and religious capacities under a variety of titles.{{ref label|Titles|a|}} He was theoretically responsible only to [[God in Islam|God]] and [[divine law]] (the Islamic {{lang|ota-Arab|شریعت}} ''şeriat'', known in Arabic as {{lang|ar|شريعة}} ''[[sharia]]''), of which he was the chief executor. His heavenly mandate ([[Kut (mythology)|Kut]]) was reflected in Islamic titles such as "shadow of God on Earth" ({{lang|ota-Arab|ظل الله في العالم}} ''ẓıll Allāh fī'l-ʿalem'') and "caliph of the face of the earth" ({{lang|ota-Arab|خلیفه روی زمین}} ''Ḫalife-i rū-yi zemīn'').<ref name="Findley">[[#Fin05|Findley 2005]], p. 115</ref> All offices were filled by his authority, and every law was issued by him in the form of a decree called ''[[Firman (decree)|firman]]'' ({{lang|ota-Arab|فرمان}}). He was the [[commander-in-chief|supreme military commander]] and had the official title to all land.<ref name="Ottoman Institutions"/> [[Osman I|Osman]] (died 1323/4) son of [[Ertuğrul]] was the first ruler of the Ottoman state, which during his reign constituted a small principality (''beylik'') in the region of [[Bithynia]] on the frontier of the [[Byzantine Empire]]. After the [[conquest of Constantinople]] in 1453 by [[Mehmed II]], Ottoman sultans came to regard themselves as the successors of the Roman Empire, hence their occasional use of the titles [[Caesar (title)|caesar]] ({{lang|ota-Arab|قیصر}} ''qayser'') of [[Rûm]], and [[emperor]],<ref name="Findley"/><ref>[[#Toy74|Toynbee 1974]], pp. 22–23</ref><ref>[[#Sta01|Stavrides 2001]], p. 20</ref> as well as the [[caliph]] of Islam.{{ref label|Caliphate|b|1}} Newly enthroned Ottoman rulers were girded with the [[Sword of Osman]], an important ceremony that served as the equivalent of European monarchs' coronation.<ref>[[#Qua05|Quataert 2005]], p. 93</ref> A non-girded sultan was not eligible to have his children included in the line of succession.<ref>[[#Osm01|d'Osman Han 2001]], "Ottoman Padishah Succession"</ref> Although absolute in theory and in principle, the sultan's powers were limited in practice. Political decisions had to take into account the opinions and attitudes of important members of the dynasty, the bureaucratic and military establishments, as well as religious leaders.<ref name="Ottoman Institutions">[[#Gla96|Glazer 1996]], "Ottoman Institutions"</ref> Beginning in the last decades of the sixteenth century, the role of the Ottoman sultans in the government of the empire began to decrease, in a period known as the [[Transformation of the Ottoman Empire]]. Despite being barred from inheriting the throne,<ref>[[#Qua05|Quataert 2005]], p. 90</ref> women of the [[Ottoman Imperial Harem|imperial harem]]—especially the reigning sultan's mother, known as the [[valide sultan]]—also played an important behind-the-scenes political role, effectively ruling the empire during the period known as the [[Sultanate of Women]].<ref>{{cite web | first = Leslie | last = Peirce | author-link = Leslie P. Peirce | title = The sultanate of women | url = http://www.channel4.com/history/microsites/H/history/e-h/harem.html | archive-url = https://web.archive.org/web/20071203045546/http://www.channel4.com/history/microsites/H/history/e-h/harem.html | publisher = [[Channel 4]] | archive-date = 2007-12-03 | access-date = 2009-04-18}}</ref> [[Constitutional monarchy|Constitutionalism]] was [[First Constitutional Era|established]] during the reign [[Abdul Hamid II]], who thus became the empire's last absolute ruler and its reluctant first constitutional monarch.<ref>[[#Gla96|Glazer 1996]], "External Threats and Internal Transformations"</ref> Although Abdul Hamid II abolished the [[General Assembly of the Ottoman Empire|parliament]] and the [[Constitution of the Ottoman Empire|constitution]] to return to personal rule in 1878, he was again forced in 1908 to [[Second Constitutional Era|reinstall constitutionalism]] and was [[31 March incident|deposed]]. Since 2021, the head of the [[Osmanoğlu family]] has been [[Harun Osman]], a great-grandson of Abdul Hamid II.<ref>{{cite web |url=https://www.dailysabah.com/turkey/last-heir-to-ottoman-throne-passes-away-at-90/news |title=Last heir to Ottoman throne passes away at 90 |website=Daily Sabah |date=19 January 2021 }}</ref> ==List of sultans== [[File:Sultans of the Ottoman Dynasty.jpg|thumb|Poster showing sultans of the Ottoman dynasty, from Osman I (upper left corner) to Mehmed V (large portrait in the center)]] {{see also|Ottoman family tree|List of burial places of Ottoman sultans}} The table below lists Ottoman sultans, as well as the last Ottoman caliph, in chronological order. The [[tughra]]s were the calligraphic seals or signatures used by Ottoman sultans. They were displayed on all official documents as well as on coins, and were far more important in identifying a sultan than his portrait. The "Notes" column contains information on each sultan's parentage and fate. Early Ottomans practiced what historian Quataert has described as "[[survival of the fittest]], not eldest, son": when a sultan died, his sons had to fight each other for the throne until a victor emerged. Because of the infighting and numerous [[fratricide]]s that occurred, there was often a time gap between a sultan's death date and the accession date of his successor.<ref>[[#Qua05|Quataert 2005]], p. 91</ref> In 1617, the [[Line of succession to the Ottoman throne|law of succession]] changed from survival of the fittest to a system based on [[agnatic seniority]] ({{lang|ota-Arab|اکبریت}} ''ekberiyet''), whereby the throne went to the oldest male of the family. This in turn explains why from the 17th century onwards a deceased sultan was rarely succeeded by his own son, but usually by an uncle or brother.<ref>[[#Qua05|Quataert 2005]], p. 92</ref> Agnatic seniority was retained until the [[Abolition of the Ottoman Sultanate|abolition of the sultanate]], despite unsuccessful attempts in the 19th century to replace it with [[primogeniture]].<ref>[[#Kar05|Karateke 2005]], pp. 37–54</ref> Note that pretenders and co-claimants during the [[Ottoman Interregnum]] are also listed here, but they are not included in the formal numbering of sultans. {| class="wikitable" style="width:100%; text-align:center;" |- ! width="5%" | No. ! width="12%" | Sultan ! width="80px" | Portrait ! width="28%" | Reign ! width="80px" | [[Tughra]] ! width="30%" | Notes ! width="100px" | Coinage |- | colspan="7" style="background:#B9B9B9" | [[Rise of the Ottoman Empire]]<br />{{small|(1299–1453)}} |- | 1 | '''[[Osman I]]''' | [[File:I Osman.jpg|100px]] | {{Circa}} 1299 – c. 1324<ref name="Basic Books">[[#Fin07|Finkel 2007]], p. 33.</ref><br/>{{small|(25 years~)}} | {{n/a}}{{ref label|Tughra|c|1}} | align="left" | *Son of [[Ertuğrul|Ertuğrul Bey]]<ref name=coin>[[#Kaf95|Kafadar 1995]], pp. 60, 122.</ref> and an unknown woman.<ref name=lm>[[#Low03|Lowry 2003]], p. 153.</ref> *Reigned until his death. | [[File:Osman Gazi Coin.jpg|180px]] |- | 2 | '''[[Orhan]]''' | [[File:Metehanzade orhangazi.jpg|100px]] | c. 1324 – March 1362<br/>{{small|(38 years~)}} | [[File:Tughra of Orhan.svg|100px|Tughra of Orhan]] | align="left" | *Son of Osman I and [[Malhun Hatun]] (unclear).<ref name=lm/> *Reigned until his death. | [[File:Orhan Gazi Akçe.jpg|180px]] |- | 3 | '''[[Murad I]]'''{{ref label|Caliphate|b|2}} | [[File:Murad I.jpg|100px]] | March 1362 – [[Battle of Kosovo|15 June 1389]]<br/>{{small|({{age in years and months|1362|3|1|1389|6|15}})}} | [[File:Tughra of Murad I.svg|100px|Tughra of Murad I]] | align="left" | *Son of Orhan and [[Nilüfer Hatun]].<ref name=lm/> *Reigned until his death. *Killed on the battlefield at the [[Battle of Kosovo|Battle of Kosovo on June 15, 1389]]. | [[File:1555 osmanli 1 murat nm nd.jpg|180px]] |- | 4 | '''[[Bayezid I]]''' | [[File:Baiazeth. P. IIII.jpg|100px]] | [[Battle of Kosovo|15 June 1389]] – [[Battle of Ankara|20 July 1402]]<br/>{{small|({{ayd|1389|6|15|1402|7|20}})}} | [[File:Tughra of Bayezid I.svg|100px|Tughra of Bayezid I]] | align="left" | *Son of Murad I and [[Gülçiçek Hatun]].<ref name=lm/> *Captured on the battlefield at the [[Battle of Ankara]] against [[Timur]]. *Died in captivity in [[Akşehir]] on 8 March 1403. | [[File:Bayezid I AR akce.png|180px]] |- | colspan="7" style="background:#B9B9B9" | [[Ottoman Interregnum]]{{ref label|Interregnum|d|}}<br />{{small|([[Battle of Ankara|20 July 1402]] – [[Battle of Çamurlu|5 July 1413]])}} |- | — | ''[[İsa Çelebi]]'' | [[File:İsa Çelebi.jpg|100px]] | January – March/May 1403<br/>{{small|(3–5 months)}} | {{n/a}} | align="left" | *Co-sultan of Anatolia *After the [[Battle of Ankara]], [[İsa Çelebi]] defeated [[Musa Çelebi]] and took the western Anatolian territories for approximately two years. *Defeated by [[Mehmed Çelebi]] in the [[Battle of Ulubad]] in March or May 1403. *Strangled in September 1403. | {{n/a}} |- | — | ''[[Süleyman Çelebi]]''{{efn|Contemporary sources mention him as a legitimate sultan, but this view is not accepted today.}} | [[File:Suleyman Celebi (166345075).jpg|100px]] | [[Battle of Ankara|20 July 1402]] –<br/>17 February 1411<ref name="Jor09">[[#Jor09|Jorga 2009]], p. 314.</ref><br/>{{small|({{ayd|1402|7|20|1411|2|17}})}} | [[File:Tughra of Süleyman Çelebi.png|100px]] | align="left" | *Acquired the title of ''The Sultan of [[Rumelia]]'' for the European portion of the empire, a short period after the Ottoman defeat at Ankara. *Murdered on 17 February 1411.<ref name=Jor09/> | [[File:Süleyman Çelebi coin 1404.png|180px]] |- | — | ''[[Musa Çelebi]]'' | [[File:Paolo Veronese (Nachfolger) - Bildnis des Sultans Moise - 2238 - Bavarian State Painting Collections.jpg|100px]] | 18 February 1411 –<br/>5 July 1413<ref name="vonH">[[#vonH|von Hammer]], pp. 58–60.</ref><br/>{{small|({{ayd|1411|2|18|1413|7|5}})}} | {{n/a}} | align="left" | *Acquired the title of ''The Sultan of [[Rumelia]]'' for the European portion of the empire<ref>Prof. Yaşar Yüce-Prof. Ali Sevim: ''Türkiye tarihi Cilt II'', AKDTYKTTK Yayınları, İstanbul, 1991 pp 74–75</ref> on 18 February 1411, just after the death of [[Süleyman Çelebi]]. *Killed on 5 July 1413 by [[Mehmed Çelebi]]'s forces in the battle of ''Çamurlu Derbent'' near [[Samokov]] in [[Bulgaria]].<ref name="vonH"/> | [[File:Akçe - Musa Çelebi.png|180px]] |- | — | [[Mehmed I|''Mehmed Çelebi'']] | [[File:Mehmed I miniature.jpg|100px]] | 1403 – [[Battle of Çamurlu|5 July 1413]]<br/>{{small|(10 years)}} | {{n/a}} | align="left" | *Acquired the control of Eastern [[Anatolia]] as co-Sultan after the [[Battle of Ankara]]. *Defeated [[İsa Çelebi]] in the battle of [[Ulubat]] in 1405. *Became the sole ruler of Anatolia upon İsa's death in 1406. *Acquired the title of [[Mehmed I|Ottoman Sultan Mehmed I Khan]] upon [[Musa Çelebi|Musa]]'s death. | [[File:Akçe - Mehmed Çelebi in the name of Timur.png|180px]] |- | colspan="7" style="background:#B9B9B9" | Sultanate resumed |- | 5 | '''[[Mehmed I]]''' | [[File:Mehmed I miniature.jpg|100px]] | [[Battle of Çamurlu|5 July 1413]] – 26 May 1421<br/>{{small|({{ayd|1413|7|5|1421|5|26}})}} | [[File:Tughra of Mehmed I.svg|100px|Tughra of Mehmed I]] | align="left" | *Son of Bayezid I and [[Devlet Hatun]].<ref name=lm/> *Reigned until his death. | {{n/a}} |- | — | ''[[Mustafa Çelebi]]'' | {{n/a}} | January 1419 – May 1422<br/>{{small|({{age in years and months|1419|1|1|1422|5|1}})}} | {{n/a}} | align="left" | *Sultan of Rumelia *Son of [[Bayezid I]] *Executed by [[Murad II]] | [[File:Akçe - Mustafa Çelebi.png|180px]] |- | 6 | '''[[Murad II]]''' | [[File:Paolo Veronese (Nachfolger) - Sultan Murad II. - 2237 - Bavarian State Painting Collections.jpg|100px]] | 25 June 1421 –<br/>August 1444<br/>{{small|({{age in years and months|1421|6|25|1444|8|1}})}} | [[File:Tughra of Murad II.svg|100px|Tughra of Murad II]] | align="left" | *Son of Mehmed I and [[Emine Hatun]].<ref name=lm/> *Abdicated of his own free will in favour of his son [[Mehmed II]]. | [[File:Akçe of Murad II Obverse.JPG|80px]][[File:Akçe of Murad II Reverse.JPG|80px]] |- | 7 | '''[[Mehmed II]]''' | [[File:Bellini, Gentile - Sultan Mehmet II.jpg|100px]] | August 1444 –<br/>September 1446<br/>{{small|({{age in years and months|1444|8|1|1446|9|1}})}} | [[File:Tughra of Mehmed II.svg|100px|Tughra of Mehmed II]] | align="left" | *First reign *Son of Murad II and [[Hüma Hatun]].<ref name=lm/> *Surrendered the throne to his father after having asked him to return to power, along with rising threats from Janissaries. | [[File:Akce_-_Mehmed_II_First_reign.png|180px]] |- | (6) | '''Murad II''' | [[File:Paolo Veronese (Nachfolger) - Sultan Murad II. - 2237 - Bavarian State Painting Collections.jpg|100px]] | September 1446 –<br/>3 February 1451<br/>{{small|({{age in years and months|1446|9|1|1451|2|3}})}} | [[File:Tughra of Murad II.svg|100px|Tughra of Murad II]] | align="left" | *Second reign *Forced to return to the throne following a [[Janissary]] insurgence.<ref>[[#Kaf95|Kafadar 1995]], p. xix</ref> *Reigned until his death. | {{n/a}} |- | colspan="7" style="background:#B9B9B9" | [[Growth of the Ottoman Empire]]<br />{{small|(1453–1550)}} |- | (7) | '''Mehmed II''' | [[File:Bellini, Gentile - Sultan Mehmet II.jpg|100px]] | 3 February 1451 –<br/>3 May 1481<br/>{{small|({{ayd|1451|2|3|1481|5|3}})}} | [[File:Tughra of Mehmed II.svg|100px|Tughra of Mehmed II]] | align="left" | *Second reign *[[Fall of Constantinople|Conquered Constantinople]] in 1453. *Reigned until his death. | [[File:Coin of Mehmed II 1451, second reign.png|180px]] |- | 8 | '''[[Bayezid II]]''' | [[File:Beyazid II.jpg|100px]] | 19 May 1481 –<br/>25 April 1512<br/>{{small|({{ayd|1481|5|19|1512|4|25}})}} | [[File:Tughra of Bayezid II.svg|100px|Tughra of Bayezid II]] | align="left" | *Son of Mehmed II and [[Gülbahar Hatun (mother of Bayezid II)|Gülbahar Hatun]].<ref name=lm/> *Abdicated. *Died near [[Didymoteicho]] on 26 May 1512. | [[File:1692 osmanli 2 beyazid ankara 886.jpg|180px]] |- | — | ''[[Cem Sultan]]'' | [[File:Cem-in-italy.jpg|100px]] | 28 May – 20 June 1481<br/>{{small|({{ayd|1481|5|28|1481|6|20}})}} | [[File:Cem Sultan Tughra.png|100px|Tughra of Cem]] | align="left" | *Son of Mehmed II *Acquired the title Cem bin Mehmed Han.<ref>[[Turkish Language Association]], (1960), ''Belleten'', p. 467 (in Turkish)</ref> *Died in exile | [[File:Akçe - Cem Sultan.png|180px]] |- | 9 | '''[[Selim I]]''' | [[File:Nakkaş Selim.jpg|100px]] | 25 April 1512 –<br/>21 September 1520<br/>{{small|({{ayd|1512|4|25|1520|9|21}})}} | [[File:Tughra of Padishah Yavuz Sultan Selim.png|100px|Tughra of Selim I]] | align="left" | * [[Ottoman–Mamluk War (1516–17)|Conquered Mamluks]] in 1516–1517. * First [[Ottoman Caliph]]. *Son of Bayezid II and [[Gülbahar Hatun (mother of Selim I)|Gülbahar Hatun]]. *Reigned until his death. | [[File:Akçe of Selim I Constantinople mint 1512.jpg|180px]] |- | 10 | '''[[Suleiman the Magnificent|Suleiman I]]''' | [[File:EmperorSuleiman.jpg|100px]] | 30 September 1520 –<br/>6 September 1566<br/>{{small|({{ayd|1520|9|30|1566|9|6}})}} | [[File:Tughra of Suleiman I the Magnificent.svg|100px|Tughra of Suleiman I]] | align="left" | *Son of Selim I and [[Hafsa Sultan]]. *Died of natural causes in his tent during the [[Siege of Szigetvár]] in 1566.<ref name= AG-BM-encyc>{{Cite book |last=Ágoston |first=Gábor |editor-last=Ágoston |editor-first=Gábor |editor-first2= Bruce |editor-last2= Masters |title=Encyclopedia of the Ottoman Empire |chapter=Süleyman I |date=2009}}</ref> | [[File:Sultani of Suleiman I, 1520.jpg|180px]] |- | colspan="7" style="background:#B9B9B9" | [[Transformation of the Ottoman Empire]]<br />{{small|(1550–1700)}} |- | 11 | '''[[Selim II]]''' | [[File:Portrait Of Sultan Selim II.jpg|100px]] | 29 September 1566 –<br/>15 December 1574<br/>{{small|({{ayd|1566|9|29|1574|12|15}})}} | [[File:Tughra of Selim II.svg|100px|Tughra of Selim II]] | align="left" | *Son of Suleiman I and [[Hürrem Sultan]]. *Reigned until his death. | [[File:Sultani LACMA M.2006.143.1 (2 of 2).jpg|80px]][[File:Sultani LACMA M.2006.143.1 (1 of 2).jpg|80px]] |- | 12 | '''[[Murad III]]''' | [[File:Sultan Murad III.jpeg|100px]] | 27 December 1574 –<br/>16 January 1595<br/>{{small|({{ayd|1574|12|27|1595|1|16}})}} | [[File:Tughra of Murad III.svg|100px|Tughra of Murad III]] | align="left" | *Son of Selim II and [[Nurbanu Sultan]]. *Reigned until his death. | [[File:Sequin Murad III 1576.jpg|180px]] |- | 13 | '''[[Mehmed III]]''' | [[File:Sultan Mehmet III of the Ottoman Empire.jpg|100px]] | 16 January 1595 –<br/>22 December 1603<br/>{{small|({{ayd|1595|1|16|1603|12|22}})}} | [[File:Tughra of Mehmed III.svg|100px|Tughra of Mehmed III]] | align="left" | *Son of Murad III and [[Safiye Sultan (mother of Mehmed III)|Safiye Sultan]]. *Reigned until his death | [[File:Coin of Mehmed III.png|180px]] |- | 14 | '''[[Ahmed I]]''' | [[File:صورة للشاهزاده أحمد 2013-12-19 09-18.jpg|100px]] | 22 December 1603 –<br/>22 November 1617<br/>{{small|({{ayd|1603|12|22|1617|11|22}})}} | [[File:Tughra of Ahmed I.JPG|100px|Tughra of Ahmed I]] | align="left" | *Son of Mehmed III and [[Handan Sultan]]. *Reigned until his death. | [[File:Post-medieval coin, Uncertain denomination of Ahmed I (FindID 489958).jpg|180px]] |- | 15 | '''[[Mustafa I]]''' | [[File:Mustafa I portrait.jpg|100px]] | 22 November 1617 –<br/>26 February 1618<br/>{{small|({{ayd|1617|11|22|1618|2|26}})}} | [[File:Tughra of Mustafa I.JPG|100px|Tughra of Mustafa I]] | align="left" | *Son of [[Mehmed III]] and [[Halime Sultan]]. *Deposed due to his mental instability in favour of his young nephew [[Osman II]]. | {{n/a}} |- | 16 | '''[[Osman II]]''' | [[File:Osman 2.jpg|100px]] | 26 February 1618 –<br/>19 May 1622<br/>{{small|({{ayd|1618|2|26|1622|05|19}})}} | [[File:Tughra of Osman II.JPG|100px|Tughra of Osman II]] | align="left" | *Son of Ahmed I and [[Mahfiruz Hatun]]. *Deposed in a [[Janissary]] riot on 19 May 1622. *Murdered on 20 May 1622 by the [[Grand Vizier]] [[Kara Davud Pasha]]. | [[File:Sultani - Osman II.jpg|180px]] |- | (15) | '''Mustafa I''' | [[File:Mustafa I portrait.jpg|100px]] | 20 May 1622 –<br/>10 September 1623<br/>{{small|({{ayd|1622|05|20|1623|9|10}})}} | [[File:Tughra of Mustafa I.JPG|100px|Tughra of Mustafa I]] | align="left" | *Second reign. *Returned to the throne after the assassination of his nephew [[Osman II]]. *Deposed due to his poor mental health and confined until his death in [[Istanbul]] on 20 January 1639. | {{n/a}} |- | 17 | '''[[Murad IV]]''' | [[File:Murad IV.jpg|100px]] | 10 September 1623 –<br/>8 February 1640<br/>{{small|({{ayd|1623|9|10|1640|2|8}})}} | [[File:Tughra of Murad IV.svg|100px|Tughra of Murad IV]] | align="left" | *Son of Ahmed I and [[Kösem Sultan]]. *Ruled under the regency of his mother [[Kösem Sultan]] until 1632. *Reigned until his death. | {{n/a}} |- | 18 | '''[[Ibrahim (Ottoman sultan)|Ibrahim]]''' | [[File:Ibrahim Deli.jpg|100px]] | 9 February 1640 –<br/>8 August 1648<br/>{{small|({{ayd|1640|2|9|1648|8|8}})}} | [[File:Tughra of Ibrahim.JPG|100px|Tughra of Ibrahim]] | align="left" | *Son of Ahmed I and [[Kösem Sultan]]. *Deposed on 8 August 1648 in a coup led by the [[List of Sheikh-ul-Islams of the Ottoman Empire|Sheikh ul-Islam]]. *Strangled in [[Istanbul]] on 18 August 1648 at the behest of the [[Grand Vizier]] [[Mawlawi Order|Mevlevî]] Mehmed Paşa ''(Sofu Mehmed Pasha)''. | {{n/a}} |- | 19 | '''[[Mehmed IV]]''' | [[File:Sultan Mehmed IV (2).jpg|100px]] | 8 August 1648 –<br/>8 November 1687<br/>{{small|({{ayd|1648|8|8|1687|11|8}})}} | [[File:Tughra of Mehmed IV.png|100px|Tughra of Mehmed IV]] | align="left" | *Son of Ibrahim and [[Turhan Sultan]]. *Ruled under the regency of his grandmother [[Kösem Sultan]] until 1651. *Ruled under the regency of his mother [[Turhan Sultan]] from 1651 until 1656. *Deposed on 8 November 1687 following the Ottoman defeat at the [[Battle of Mohács (1687)|Second Battle of Mohács]]. *Died in [[Edirne]] on 6 January 1693. | [[File:Osmanen- Mehmed IV. - Münzkabinett, Berlin - 5556643.jpg|180px]] |- | 20 | '''[[Suleiman II of the Ottoman Empire|Suleiman II]]''' | [[File:II Suleyman.jpg|100px]] | 8 November 1687 –<br/>22 June 1691<br/>{{small|({{ayd|1687|11|8|1691|6|22}})}} | [[File:Tughra of Suleiman II.svg|100px|Tughra of Suleiman II]] | align="left" | *Son of Ibrahim and [[Aşub Sultan|Dilaşub Sultan]]. *Reigned until his death. | [[File:Kupfer Not-Akce 1099 H., Qustantiniya (Konstantinopel-Istanbul)-210-00912q00.jpg|180px]] |- | 21 | '''[[Ahmed II]]''' | [[File:Ahmed II Sahand Ace.jpg|134x134px]] | 22 June 1691 –<br/>6 February 1695<br/>{{small|({{ayd|1691|6|22|1695|2|6}})}} | [[File:Tughra of Ahmed II.JPG|100px|Tughra of Ahmed II]] | align="left" | *Son of Ibrahim and [[Muazzez Sultan]]. *Reigned until his death. | {{n/a}} |- | 22 | '''[[Mustafa II]]''' | [[File:Mustafa II dressed in full armour.JPG|100px]] | 6 February 1695 –<br/>22 August 1703<br/>{{small|({{ayd|1695|2|6|1703|8|22}})}} | [[File:Tughra of Mustafa II.JPG|100px|Tughra of Mustafa II]] | align="left" | *Son of Mehmed IV and [[Gülnuş Sultan]]. *Deposed on 22 August 1703 by a [[Janissary]] uprising known as the [[Edirne event|Edirne Event]]. *Died in Istanbul on 8 January 1704. | [[File:1 Kuruș Mustafa II of Ottoman 1695-1704.png|180px]] |- | colspan="7" style="background:#B9B9B9" | [[Stagnation and reform of the Ottoman Empire]]<br />{{small|(1700–1827)}} |- | 23 | '''[[Ahmed III]]''' | [[File:Portrait of Sultan Ahmed III (1673–1736), three-quarter-length, standing, with a view onto the Bosphorus and the Hagia Sophia by Jean-Baptiste Vanmour.jpg|100px]] | 22 August 1703 –<br/>[[Patrona Halil rebellion|1 October 1730]]<br/>{{small|({{ayd|1703|8|22|1730|10|1}})}} | [[File:Tughra of Ahmed III.JPG|100px|Tughra of Ahmed III]] | align="left" | *Son of Mehmed IV and [[Gülnuş Sultan]]. *Deposed in consequence of the [[Janissary]] rebellion led by [[Patrona Halil]]. *Died on 1 July 1736. | [[File:Sultani of Ahmed III, 1703.jpg|180px]] |- | 24 | '''[[Mahmud I]]''' | [[File:Sultan Mahmud I – Jean Baptiste Vanmour.jpg (cropped).jpg|100px]] | 2 October 1730 –<br/>13 December 1754<br/>{{small|({{ayd|1730|10|2|1754|12|13}})}} | [[File:Tughra of Mahmud I.JPG|100px|Tughra of Mahmud I]] | align="left" | *Son of Mustafa II and [[Saliha Sultan (mother of Mahmud I)|Saliha Sultan]]. *Reigned until his death. | [[File:Sequin of Mahmud I.jpg|180px]] |- | 25 | '''[[Osman III]]''' | [[File:III.Osman.webp|100px]] | 13 December 1754 –<br/>30 October 1757<br/>{{small|({{ayd|1754|12|13|1757|10|30}})}} | [[File:Tughra of Osman III.JPG|100px|Tughra of Osman III]] | align="left" | *Son of Mustafa II and [[Şehsuvar Sultan]]. *Reigned until his death. | [[File:Turchia, osman III, moneta d'oro, 1754-1757.JPG|100px]] |- | 26 | '''[[Mustafa III]]''' | [[File:Sultan Mustafa III.jpg|100px]] | 30 October 1757 –<br/>21 January 1774<br/>{{small|({{ayd|1757|10|30|1774|1|21}})}} | [[File:Tughra of Mustafa III.svg|100px|Tughra of Mustafa III]] | align="left" | *Son of Ahmed III and [[Mihrişah Kadın (mother of Mustafa III)|Mihrişah Kadın]]. *Reigned until his death. |[[File:1 Piastre 1183 Mustafa III (obv)-8477.jpg|80px]][[File:1 Piastre 1183 Mustafa III (rev)-8478.jpg|80px]] |- | 27 | '''[[Abdul Hamid I]]''' | [[File:Portrait of Abdülhamid I of the Ottoman Empire.jpg|100px]] | 21 January 1774 –<br/>7 April 1789<br/>{{small|({{ayd|1774|1|21|1789|4|7}})}} | [[File:Tughra of Abdülhamid I.svg|100px|Tughra of Abdul Hamid I]] | align="left" | *Son of Ahmed III and [[Rabia Şermi Kadın]]. *Reigned until his death. | [[File:M64 10para Constantinople KM383 1ar85 (8645875592).jpg|180px]] |- | 28 | '''[[Selim III]]''' | [[File:Joseph Warnia-Zarzecki - Sultan Selim III - Google Art Project.jpg|100px]] | 7 April 1789 –<br/>[[Ottoman coups of 1807–1808|29 May 1807]]<br/>{{small|({{ayd|1789|4|7|1807|5|29}})}} | [[File:Tughra of Selim III.JPG|100px|Tughra of Selim III]] | align="left" | *Son of Mustafa III and [[Mihrişah Sultan (mother of Selim III)|Mihrişah Sultan]]. *Deposed as a result of the [[Ottoman coups of 1807–08|Janissary revolt]] led by [[Kabakçı Mustafa]] against his reforms. *Assassinated in Istanbul on 28 July 1808 at the behest of Mustafa IV. | [[File:Rial Tunisien - Selim III - 1215 AH - 1800 AD.jpg|180px]] |- | 29 | '''[[Mustafa IV]]''' | [[File:IV. Mustafa.jpg|100px]] | 29 May 1807 –<br/>[[Ottoman coups of 1807–1808|28 July 1808]]<br/>{{small|({{ayd|1807|5|29|1808|7|28}})}} | [[File:Tughra of Mustafa IV.JPG|100px|Tughra of Mustafa IV]] | align="left" | *Son of Abdul Hamid I and [[Sineperver Sultan]]. *Deposed in an [[Ottoman coups of 1807–08|insurrection]] led by [[Alemdar Mustafa Pasha]]. *Executed in Istanbul on 17 November 1808 by order of Mahmud II. |{{n/a}} |- | colspan="7" style="background:#B9B9B9" | [[Decline and modernization of the Ottoman Empire|Modernization of the Ottoman Empire]]<br />{{small|(1827–1908)}} |- | 30 | '''[[Mahmud II]]''' | [[File:Mahmud II.jpg|100px]] | 28 July 1808 –<br/>1 July 1839<br/>{{small|({{ayd|1808|7|28|1839|7|1}})}} | [[File:Tughra Mahmud II bw.svg|100px|Tughra of Mahmud II]] | align="left" | *Son of Abdul Hamid I and [[Nakşidil Sultan]]. *Disbanded the [[Janissaries]] in consequence of the [[Auspicious Incident]] in 1826. *Reigned until his death. | [[File:2 Budju of Ottoman Algeria - Mahmud II 1823.png|180px]] |- | 31 | '''[[Abdülmecid I|Abdul Mejid I]]''' | [[File:Abdulmejid portrait.jpg|100px]] | 1 July 1839 –<br/>25 June 1861<br/>{{small|({{ayd|1839|7|1|1861|6|25}})}} | [[File:Tughra of Abdülmecid I.svg|100px|Tughra of Abdulmejid I]] | align="left" | *Son of Mahmud II and [[Bezmiâlem Sultan]]. *Proclaimed the [[Hatt-i Sharif|Imperial Edict of Gülhane ''(Tanzimât Fermânı)'']] that launched the [[Tanzimat]] period of reforms and reorganization on 3 November 1839 at the behest of reformist [[Grand vizier]] [[Mustafa Reşid Pasha]]. *Accepted the [[Hatt-ı Hümayun|Islâhat Hatt-ı Hümayun (Imperial Reform Edict) ''(Islâhat Fermânı)'']] on 18 February 1856. *Reigned until his death. | [[File:20 Piastres 1270 Abdülmecid I (obv)-8467.jpg|85px]][[File:20 Piastres 1270 Abdülmecid I (rev)-8468.jpg|85px]] |- | 32 | '''[[Abdulaziz|Abdul Aziz]]''' | [[File:Sultan Abdulaziz.jpg|100px]] | 25 June 1861 –<br/>[[1876 Turkish coup d'état|30 May 1876]]<br/>{{small|({{ayd|1861|6|25|1876|5|30}})}} | [[File:Tughra of Abdülaziz.svg|100px|Tughra of Abdulaziz]] | align="left" | *Son of Mahmud II and [[Pertevniyal Sultan]]. *Deposed by his ministers. *Found dead (suicide or murder) five days later. | [[File:20 kurus Abdulaziz 1862.png|180px]] |- | 33 | '''[[Murad V]]''' | [[File:Sultan Murad V., 1876.jpg|100px]]<!--This is the only drawing/picture of him (so far?) while he was a sultan, thus please do not remove this with other pictures, where he still was a prince--> | 30 May – 31 August 1876<br/>{{small|({{ayd|1876|5|30|1876|8|31}})}} | [[File:Tughra of Murad V.svg|100px|Tughra of Murad V]] | align="left" | *Son of Abdulmejid I and [[Şevkefza Sultan]]. *Deposed due to his ill mental health. *Ordered to reside in [[Çırağan Palace]] where he died on 29 August 1904. | {{n/a}} |- | 34 | '''[[Abdul Hamid II]]''' | [[File:Sultan Gazi Abdül Hamid II - السلطان الغازي عبد الحميد الثاني.png|100px]] | 31 August 1876 –<br/>[[31 March Incident|27 April 1909]]<br/>{{small|({{ayd|1876|8|31|1909|4|27}})}} | [[File:Tughra of Abdülhamid II.svg|100px|Tughra of Abdul Hamid II]] | align="left" | *Son of Abdulmejid I and [[Tirimüjgan Kadın]] (later became the adoptive son of [[Perestu Kadın|Rahime Perestu Sultan]]). *Reluctantly allowed the [[First Constitutional Era]] on 23 November 1876 and then suspended it on 13 February 1878. *Forced to [[Second Constitutional Era|restore the Constitution]] on 3 July 1908. *Deposed after the [[31 March incident]]. *Confined to [[Beylerbeyi Palace]] where he died on 10 February 1918. | [[File:20 kurus Abdul Hamid II - 1877.png|180px]] |- | 35 | '''[[Mehmed V|Mehmed V Reşâd]]''' | [[File:Sultan Muhammed Chan V., Kaiser der Osmanen 1915 C. Pietzner.jpg|100px]] | 27 April 1909 –<br/>3 July 1918<br/>{{small|({{ayd|1909|4|27|1918|7|3}})}} | [[File:Tughra of Mehmed V.svg|80px|Tughra of Mehmed V]] | align="left" | *Son of Abdulmejid I and [[Gülcemal Kadın]] (later became the adoptive son of [[Servetseza Kadın]]). *Reigned as a [[figurehead]] of [[Mehmed Talat]], [[İsmail Enver]], and [[Ahmed Djemal|Ahmed Cemal]] [[Three Pashas|Pashas]]. *Reigned until his death. | [[File:Lira of Mehmed V, 1911.jpg|180px]] |- | 36 | '''[[Mehmed VI|Mehmed VI Vahideddin]]''' | [[File:Sultan Mehmed VI of the Ottoman Empire.jpg|100px]] | 4 July 1918 –<br/>[[Abolition of the Ottoman sultanate|1 November 1922]]<br/>{{small|({{ayd|1918|7|4|1922|11|1}})}} | [[File:Tughra of Mehmed VI.svg|100px|Tughra of Mehmed VI]] | align="left" | *Son of Abdulmejid I and [[Gülistu Kadın]] (later became the adoptive son of [[Şayeste Hanım]]) *[[Abolition of the Ottoman Sultanate|Sultanate abolished]]. *Left [[Istanbul]] on 17 November 1922. *Died in [[exile]] in [[Sanremo]], [[Kingdom of Italy|Italy]] on 16 May 1926. | [[File:36-1336-01-500K-kost-au.jpg|180px]] |- | colspan="7" style="background:#B9B9B9" | [[Ottoman Caliphate#Abolition|Caliph]] under the [[Grand National Assembly of Turkey]]<br />{{small|(1 November 1922 – 3 March 1924)}} |- | — | '''[[Abdulmejid II|Abdul Mejid II]]''' | [[File:Portrait Caliph Abdulmecid II.jpg|100px]] | 19 November 1922 –<br/>[[Abolition of the Caliphate|3 March 1924]]<br/>{{small|({{ayd|1922|11|18|1924|3|3}})}} | —<br />{{ref label|Tughra|c|2}} | align="left" | *Son of Abdulaziz and [[Hayranidil Kadın]];<ref>[[#Asi92|Aşiroğlu 1992]], p. 13</ref> *[[Exile]]d after the [[abolition of the Caliphate]];<ref>[[#Asi92|Aşiroğlu 1992]], p. 17</ref> *Died in [[Paris]], [[France]] on 23 August 1944.<ref>[[#Asi92|Aşiroğlu 1992]], p. 14</ref> | — |} '''Notes''' {{notelist}} ==See also== *[[Line of succession to the Ottoman throne]] *[[Ottoman family tree (simplified)|Ottoman sultan family tree]] *[[Ottoman family tree]] (more detailed) *[[Valide sultan]] *[[List of Ottoman grand viziers]] ==Notes== {{refbegin}} :'''a'''{{note|Titles}}: The [[Ottoman titles|full style]] of the Ottoman ruler was complex, as it was composed of several titles and evolved over the centuries. The title of [[sultan]] was used continuously by all rulers almost from the beginning. However, because it was widespread in the Muslim world, the Ottomans quickly adopted variations of it to dissociate themselves from other Muslim rulers of lesser status. [[Murad I]], the third Ottoman monarch, styled himself ''sultân-ı âzam'' ({{lang|ota|سلطان اعظم}}, the most exalted sultan) and ''hüdavendigar'' ({{lang|ota|خداوندگار}}, emperor), titles used by the Anatolian [[Seljuq dynasty|Seljuqs]] and the Mongol [[Ilkhanate|Ilkhanids]] respectively. His son [[Bayezid I]] adopted the style ''Sultan of Rûm'', [[Rûm]] being an old Islamic name for the Roman Empire. The combining of the Islamic and Central Asian heritages of the Ottomans led to the adoption of the title that became the standard designation of the Ottoman ruler: ''Sultan [Name] Khan''.<ref>[[#Pei93|Peirce 1993]], pp. 158–159</ref> Ironically, although the title of sultan is most often associated in the [[Western world]] with the Ottomans, people within Turkey generally use the title of ''[[padishah]]'' far more frequently when referring to rulers of the Ottoman Dynasty.<ref>{{cite magazine | last = M'Gregor | first = J. |date=July 1854 | title = The Race, Religions, and Government of the Ottoman Empire |magazine=The Eclectic Magazine of Foreign Literature, Science, and Art | volume = 32 |page=376 | publisher = Leavitt, Trow, & Co. | location = New York | oclc = 6298914 | url = https://books.google.com/books?id=1MYRAAAAYAAJ | access-date = 2009-04-25}}</ref> :'''b'''{{note label|Caliphate||1}}{{note label|Caliphate||2}}{{note label|Caliphate||3}}: The [[Ottoman Caliphate]] symbolized their spiritual power, whereas the sultanate represented their temporal power. According to Ottoman [[historiography]], [[Murad I]] adopted the title of caliph during his reign (1362 to 1389), and [[Selim I]] later strengthened the caliphal authority during his [[Ottoman–Mamluk War (1516–17)|conquest of Egypt]] in 1516-1517. However, the general consensus among modern scholars is that Ottoman rulers had used the title of caliph before the conquest of Egypt, as early as during the reign of [[Murad I]] (1362–1389), who brought most of the Balkans under Ottoman rule and established the title of sultan in 1383. It is currently agreed that the caliphate "disappeared" for two-and-a-half centuries, before being revived with the [[Treaty of Küçük Kaynarca]], signed between the Ottoman Empire and [[Catherine II of Russia]] in 1774. The treaty was highly symbolic, since it marked the first international recognition of the Ottomans' claim to the caliphate. Although the treaty made official the Ottoman Empire's loss of the [[Crimean Khanate]], it acknowledged the Ottoman caliph's continuing religious authority over [[Islam in Russia|Muslims in Russia]].<ref>[[#Gla03|Glassé 2003]], pp. 349–351.</ref> From the 18th century onwards, Ottoman sultans increasingly emphasized their status as caliphs in order to stir [[Pan-Islamism|Pan-Islamist]] sentiments among the empire's Muslims in the face of encroaching European imperialism. When [[World War I]] broke out, Caliph [[Mehmed V]] issued a [[1914 Ottoman jihad proclamation|proclamation]] for ''[[jihad]]'' in 1914 against the Ottoman Empire's [[Allies of World War I|Allied enemies]], unsuccessfully attempting to incite the subjects of the [[French colonial empire|French]], [[British Empire|British]] and [[Russian Empire|Russian]] empires to revolt. [[Abdul Hamid II]] was by far the Ottoman sultan who made the most use of his caliphal position, and was recognized as caliph by many Muslim heads of state, even as far away as the [[Abdul Hamid II#America and the Philippines|Philippines]]<ref>{{cite book |author=Kemal H. Karpat |title=The Politicization of Islam: Reconstructing Identity, State, Faith, and Community in the Late Ottoman State |url=https://books.google.com/books?id=PvVlS3ljx20C&q=Straus+Sulu+Ottoman&pg=PA235 |year=2001 |publisher=Oxford University Press |isbn=978-0-19-513618-0 |pages=235– }}</ref><ref>{{cite book|author=J. Robert Moskin|title=American Statecraft: The Story of the U.S. Foreign Service|url=https://books.google.com/books?id=pc5FAQAAQBAJ&q=Straus+Sulu+Ottoman&pg=PA204|date=2013|publisher=St. Martin's Press|isbn=978-1-250-03745-9|pages=204–}}</ref> and [[Sumatra]].<ref>[[#Qua05|Quataert 2005]], pp. 83–85</ref> He had his claim to the title inserted into the [[Kanûn-ı Esâsî|1876 Constitution]] (Article 4).<ref name="Toprak">[[#Top81|Toprak 1981]], pp. 44–45</ref> :'''c'''{{note label|Tughra||1}}{{note label|Tughra||2}}: [[Tughra]]s were used by 35 out of 36 Ottoman sultans, starting with [[Orhan]] in the 14th century, whose tughra has been found on two different documents. No tughra bearing the name of [[Osman I]], the founder of the empire, has ever been discovered,<ref>{{cite web | url = http://www.tugra.org/en/hakkinda.asp | title = About Tugra | access-date = 2009-02-06 | last = Mensiz | first = Ercan | publisher = Tugra.org | archive-url = https://web.archive.org/web/20071025010127/http://www.tugra.org/en/hakkinda.asp | archive-date = 2007-10-25}}</ref> although a coin with the inscription "Osman bin Ertuğrul" has been identified.<ref name=coin/> [[Abdulmejid II]], the last Ottoman Caliph, also lacked a tughra of his own, since he did not serve as [[head of state]] (that position being held by [[Mustafa Kemal Atatürk|Mustafa Kemal]], President of the newly founded Republic of Turkey) but as a religious and royal [[figurehead]]. :'''d'''{{note|Interregnum}}: The [[Ottoman Interregnum]], also known as the Ottoman Triumvirate ({{Langx|tr|Fetret Devri}}), was a period of chaos in the Ottoman Empire which lasted from 1402 to 1413. It started following the defeat and capture of [[Bayezid I]] by the [[Turkic peoples|Turco-]][[Mongols|Mongol]] warlord [[Timur|Tamerlane]] at the [[Battle of Ankara]], which was fought on 20 July 1402. Bayezid's sons fought each other for over a decade, until [[Mehmed I]] emerged as the undisputed victor in 1413.<ref>[[#Sug93|Sugar 1993]], pp. 23–27</ref> :'''e'''{{note|Dissolution}}: The [[dissolution of the Ottoman Empire]] was a gradual process which started with the abolition of the sultanate and ended with that of the caliphate 16 months later. The sultanate was formally abolished on 1 November 1922. Sultan [[Mehmed VI]] fled to [[Malta]] on 17 November aboard the British warship ''[[HMS Malaya|Malaya]]''. This event marked the end of the Ottoman ''Dynasty'', not of the Ottoman ''State'' nor of the [[Ottoman Caliphate]]. On 19 November, the [[Grand National Assembly of Turkey|Grand National Assembly]] (TBMM) elected Mehmed VI's cousin [[Abdulmejid II]], the then crown prince, as caliph.<ref>[[#Asi92|Aşiroğlu 1992]], p. 54</ref> The official end of the Ottoman State was declared through the [[Treaty of Lausanne]] (24 July 1923), which recognized the new "[[Ankara]] government," and not the old Istanbul-based Ottoman government, as representing the rightful owner and successor state. The [[Turkey|Republic of Turkey]] was proclaimed by the TBMM on 29 October 1923, with [[Mustafa Kemal Atatürk|Mustafa Kemal]] as its first [[President of Turkey|President]].<ref>[[#Gla96|Glazer 1996]], "Table A. Chronology of Major Kemalist Reforms"</ref> Although Abdulmejid II was a [[figurehead]] lacking any political power, he remained in his position of Caliph until the office of the Caliphate was abolished by the TBMM on 3 March 1924.<ref name="Toprak"/> Mehmed VI later tried unsuccessfully to reinstall himself as caliph in the [[Hejaz]].<ref>{{cite encyclopedia | last = Steffen | first = Dirk | editor = Tucker, Spencer | encyclopedia = World War I: Encyclopedia | title = Mehmed VI, Sultan | url = https://books.google.com/books?id=B1cMtKQP3P8C | access-date = 2009-05-02 | year = 2005 | series = Volume | publisher = ABC-CLIO | volume = III: M–R | location = Santa Barbara, CA | isbn = 978-1-85109-420-2 | oclc = 162287003 | page = 779}}</ref> {{refend}} ==References== {{reflist|30em}} ==Bibliography== {{Commons category|Sultans of the Ottoman Empire}} {{refbegin}} *{{cite book |last=Aşiroğlu |first=Orhan Gâzi |title=Son halife, Abdülmecid |series=Tarihin şahitleri dizisi |year=1992 |publisher=Burak Yayınevi |location=Istanbul |language=tr |isbn=978-9757645177 |oclc=32085609 |ref=Asi92}} <!-- *{{cite book |last=Duran |first=Tülay |title=Padişah Portreleri (Portraits of the Ottoman Empire's Sultans) |year=1999 |publisher=Association of Historical Research and Istanbul Research Centre |location=Sirkeci |language=tr |isbn=978-9756926079 |oclc=248496159}} --> *{{cite book |last=Findley |first=Carter V. |title=The Turks in World History |url=https://books.google.com/books?id=2_41FJ-pgRAC |access-date=2009-04-29 |year=2005 |publisher=[[Oxford University Press]] US |location=New York |isbn=978-0-19-517726-8 |oclc=54529318 |ref=Fin05}} *{{cite book |last1=Finkel |first1=Caroline |title=Osman's Dream: The History of the Ottoman Empire. |date=2007 |publisher=Basic Books |isbn=978-0465008506 |ref=Fin07}} *{{cite encyclopedia | editor = Glassé, Cyril | encyclopedia = The New Encyclopedia of Islam | title = Ottomans | url = https://books.google.com/books?id=focLrox-frUC | access-date = 2009-05-02 | year = 2003 | publisher = AltaMira Press | location = Walnut Creek, CA | isbn = 978-0-7591-0190-6 | oclc = 52611080 |ref=Gla03}} *{{cite book |last=Glazer |first=Steven A. |editor-last=Metz |editor-first=Helen Chapin |editor-link=Helen Chapin Metz |title=A Country Study: Turkey |url=https://archive.org/details/turkeycountrystu00metz |access-date=2009-04-22 |edition=5th |series=[[Library of Congress Country Studies|Country Studies]] |orig-date=Research completed January 1995 |year=1996 |publisher=Federal Research Division of the Library of Congress |location=Washington, D.C. |isbn=978-0-8444-0864-4 |oclc=33898522 |chapter=Chapter 1: Historical Setting |ref=Gla96 }} *{{cite book |last=Jorga |first=Nicholae |author-link=Nicolae Iorga |title=Geschishte des Osmanichen |others=Translated by Nilüfer Epçeli |volume=1 |publisher=Yeditepe yayınları |location=Istanbul |year=2009 |isbn=978-975-6480-17-5 |ref=Jor09}} *{{cite book |last=Kafadar |first=Cemal |title=Between Two Worlds: The Construction of the Ottoman State |url=https://books.google.com/books?id=LsP-2y7kuJkC |access-date=2009-04-18 |year=1995 |publisher=[[University of California Press]] |location=Berkeley, CA |isbn=978-0-520-20600-7 |oclc=55849447 |ref=Kaf95}} *{{cite book |last=Karateke |first=Hakan T. |editor1-last=Weismann |editor1-first=Itzchak |editor2-last=Zachs |editor2-first=Fruma |title=Ottoman Reform and Muslim Regeneration: Studies in Honour of Butrus Abu-Manneb |url=https://books.google.com/books?id=U7loMhnI5S8C |access-date=2009-05-02 |year=2005 |publisher=I.B. Tauris |location=London |isbn=978-1-85043-757-4 |oclc=60416792 |chapter=Who is the Next Ottoman Sultan? Attempts to Change the Rule of Succession during the Nineteenth Century |ref=Kar05}} *{{Cite book |last=Lindner |first=Rudi Paul |title=Nomads and Ottomans in Medieval Anatolia |publisher=Indiana University Press |date=1983 |ref=Lin83}} *{{Cite book |last=Lowry |first=Heath |title=The Nature of the Early Ottoman State |publisher=SUNY Press |date=2003 |isbn=0-7914-5636-6 |ref=Low03}} *{{cite book |last=d'Osman Han |first=Nadine Sultana |others=Foreword by Manoutchehr M. Eskandari-Qajar |title=The Legacy of Sultan Abdulhamid II: Memoirs and Biography of Sultan Selim bin Hamid Han |url=http://nadinevalidesultan.org/history.html |access-date=2009-05-02 |year=2001 |publisher=Sultana Pub |location=Santa Fe, NM |oclc=70659193 |ref=Osm01 |url-status=live |archive-url=https://web.archive.org/web/20090105170518/http://nadinevalidesultan.org/history.html |archive-date=2009-01-05 }} *{{cite book |last=Peirce |first=Leslie P. |author-link=Leslie P. Peirce |title=The Imperial Harem: Women and Sovereignty in the Ottoman Empire |url=https://books.google.com/books?id=L6-VRgVzRcUC |access-date=2009-04-19 |year=1993 |publisher=Oxford University Press US |location=New York |isbn=978-0-19-508677-5 |oclc=243767445 |ref=Pei93}} *{{cite book |last=Quataert |first=Donald |title=The Ottoman Empire, 1700–1922 |url=https://books.google.com/books?id=OX3lsOrXJGcC |access-date=2009-04-18 |edition=2nd |year=2005 |publisher=[[Cambridge University Press]] |isbn=978-0-521-83910-5 |oclc=59280221 |ref=Qua05}} *{{cite book |last=Stavrides |first=Theoharis |title=The Sultan of Vezirs: The Life and Times of the Ottoman Grand Vezir Mahmud Pasha Angelović (1453–1474) |url=https://books.google.com/books?id=ptXG0uA70lAC |access-date=2009-04-18 |year=2001 |publisher=[[Brill Publishers]] |location=Leiden |isbn=978-90-04-12106-5 |oclc=46640850 |ref=Sta01}} *{{cite book |last=Strauss |first=Johann|url=https://menadoc.bibliothek.uni-halle.de/menalib/download/pdf/2734659?originalFilename=true |year=2010 |chapter=A Constitution for a Multilingual Empire: Translations of the ''Kanun-ı Esasi'' and Other Official Texts into Minority Languages | editor=Herzog, Christoph|editor2=Malek Sharif|title= The First Ottoman Experiment in Democracy|publisher=[[Orient-Institut Istanbul]] |publication-place= [[Würzburg]] |ref=Str10}} ([http://menadoc.bibliothek.uni-halle.de/urn/urn:nbn:de:gbv:3:5-91645 info page on book] at [[Martin Luther University]]) // CITED: pp. 43–44 (PDF pp. 45–46/338). *{{cite book |last=Sugar |first=Peter F. |author-link=Peter Sugar |title=Southeastern Europe under Ottoman Rule, 1354–1804 |url=https://books.google.com/books?id=LOln4TGdDHYC |access-date=2009-04-18 |edition=3rd |year=1993 |publisher=[[University of Washington Press]] |location=Seattle |isbn=978-0-295-96033-3 |oclc=34219399 |ref=Sug93}} *{{cite book |last=Toprak |first=Binnaz |title=Islam and Political Development in Turkey |url=https://books.google.com/books?id=xIoeAAAAIAAJ |access-date=2009-04-19 |year=1981 |publisher=Brill Publishers |location=Leiden |isbn=978-90-04-06471-3 |oclc=8258992 |ref=Top81}} *{{cite book |last=Toynbee |first=Arnold J. |author-link=Arnold J. Toynbee |editor-last=Karpat |editor-first=Kemal H. |editor-link=Kemal Karpat |title=The Ottoman State and Its Place in World History |url=https://books.google.com/books?id=orEfAAAAIAAJ |access-date=2009-05-02 |series=Social, Economic and Political Studies of the Middle East |volume=11 |year=1974 |publisher=Brill Publishers |location=Leiden |isbn=978-90-04-03945-2 |oclc=1318483 |chapter=The Ottoman Empire's Place in World History |ref=Toy74}} *{{cite book |last=Uğur |first=Ali |title=Mavi Emperyalizm |trans-title=Blue Imperialism |url=http://www.kitapyurdu.com/kitap/default.asp?id=120251 |access-date=2009-04-19 |year=2007 |publisher=Çatı Publishing |location=Istanbul |isbn=978-975-8845-87-3 |oclc=221203375 |language=tr |ref=Top81}} *{{cite book |last=von Hammer |first=Joseph |author-link=Joseph von Hammer-Purgstall |title=Osmanlı Tarihi cilt I |publisher=Milliyet yayınları |location=Istanbul |others=condensed by Abdülkadir Karahan |ref=vonH}} {{refend}} {{Sultans of the Ottoman Empire|state=expanded}} {{Turkey topics}} [[زمرو:عثماني سلطنت]] [[زمرو:ترڪي ۾ رياستي سربراهه]] [[زمرو:عثماني سلطنت جا سلطان]] [[زمرو:ايشيا ۾ بادشاهن جون فهرستون]] [[زمرو:يورپ ۾ بادشاهن جون فهرستون]] [[زمرو:عثماني سلطنت سان لاڳاپيل فهرستون]] [[زمرو:فهرستون]] [[زمرو:سياست]] [[زمرو:ترڪي سان لاڳاپيل فهرستون]] [[زمرو:ايشيا جي قديم تاريخ]] [[زمرو:يورپ جي قديم تاريخ]] q3gznid0vcsrq8xkai1wb54rblcqxld 0 31723 371872 371672 2026-04-17T11:34:40Z Ibne maryam 17680 371872 wikitext text/x-wiki {{Short description|Object-oriented programming language}} {{Distinguish|Java (software platform)|JavaScript|Java |Javanese language}} {{Infobox language | name = Java | logo = Java programming language logo.svg | logo size = 121px | logo caption = | paradigm = [[Programming paradigm#Multi-paradigm|Multi-paradigm]]: [[generic programming|generic]], [[object-oriented]] ([[class-based programming|class-based]]), [[functional programming|functional]], [[imperative programming|imperative]], [[reflection (computer programming)|reflective]], [[concurrent computing|concurrent]] | year = {{Start date and age|1995|5|23}}<ref>{{cite magazine|url=https://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|title=Java's 20 Years of Innovation|magazine=Forbes|date=May 20, 2015|access-date=March 18, 2016|author=Binstock, Andrew|archive-url=https://web.archive.org/web/20160314102242/http://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|archive-date=March 14, 2016|url-status=live}}</ref> | discontinued = <!-- Set to yes if software is discontinued, otherwise omit. --> | ver layout = <!-- simple (default) or stacked --> | latest release version = {{wikidata|property|edit|reference|P548=Q2804309|P348}} | latest release date = {{start date and age|{{wikidata|qualifier|single|P548=Q2804309|P348|P577}}}} | designer = [[James Gosling]] | developer = [[Oracle Corporation]] | typing = [[type system|Static, strong, safe]], [[nominal type system|nominative]], [[manifest typing|manifest]] | memory management = [[Garbage collection (computer science)|Automatic garbage collection]] | influenced_by = [[CLU (programming language)|CLU]],<ref name="BarbaraLiskov">{{cite book |title=Program Development in Java - Abstraction, Specification, and Object-Oriented Design|author=[[Barbara Liskov]] with [[John Guttag]]|isbn=9780201657685|publisher=USA, Addison Wesley|year=2000}}</ref> [[Simula67]],<ref name="BarbaraLiskov"/> [[Lisp (programming language)|Lisp]],<ref name="BarbaraLiskov"/> [[Smalltalk]],<ref name="BarbaraLiskov"/> [[Ada (programming language)|Ada 83]], [[C++]],<ref>{{cite web|url=https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133|title=Cracking The Java Programming Interview :: 2000+ Java Interview Que/Ans|first=Harry H.|last=Chaudhary|access-date=2016-05-29|date=2014-07-28|archive-date=September 29, 2023|archive-url=https://web.archive.org/web/20230929040943/https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133#v=onepage&q&f=false|url-status=live}}</ref> [[C Sharp (programming language)|C#]],<ref>Java&nbsp;5.0 added several new language features (the [[foreach loop|enhanced for loop]], [[object type (object-oriented programming)#Autoboxing|autoboxing]], [[variadic function|varargs]] and [[Java annotation|annotations]]), after they were introduced in the similar (and competing) [[C Sharp (programming language)|C#]] language. [http://www.barrycornelius.com/papers/java5/] {{Webarchive|url=https://web.archive.org/web/20110319065438/http://www.barrycornelius.com/papers/java5/|date=March 19, 2011}} [http://www.levenez.com/lang/] {{Webarchive|url=https://web.archive.org/web/20060107162045/http://www.levenez.com/lang/|date=January 7, 2006}}</ref> [[Eiffel (programming language)|Eiffel]],<ref>{{cite web|author1=Gosling, James|author2=McGilton, Henry|title=The Java Language Environment|date=May 1996|url=https://www.oracle.com/technetwork/java/langenv-140151.html|access-date=May 6, 2014|archive-url=https://web.archive.org/web/20140506214653/http://www.oracle.com/technetwork/java/langenv-140151.html|archive-date=May 6, 2014 |url-status=live}}</ref> [[Mesa (programming language)|Mesa]],<ref>{{cite web|author1=Gosling, James|author2=Joy, Bill |author3=Steele, Guy|author4=Bracha, Gilad|title=The Java Language Specification, 2nd Edition |url=https://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|access-date=February 8, 2008|archive-url=https://web.archive.org/web/20110805051057/http://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|archive-date=August 5, 2011 |url-status=live}}</ref> [[Modula-3]],<ref>{{cite web |url=http://www.computerworld.com.au/index.php/id;1422447371;pp;3;fp;4194304;fpid;1|title=The A-Z of Programming Languages: Modula-3 |publisher=Computerworld|access-date=2010-06-09|url-status=dead|archive-url=https://web.archive.org/web/20090105145818/http://www.computerworld.com.au/index.php/id%3B1422447371%3Bpp%3B3%3Bfp%3B4194304%3Bfpid%3B1|archive-date=January 5, 2009}}</ref> [[Oberon (programming language)|Oberon]],<ref>[[Niklaus Wirth]] stated on a number of public occasions, e.g. in a lecture at the Polytechnic Museum, Moscow in September 2005 (several independent first-hand accounts in Russian exist, e.g. one with an audio recording: {{cite web|author=Filippova, Elena|title=Niklaus Wirth's lecture at the Polytechnic Museum in Moscow|date=September 22, 2005|url=http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|access-date=November 20, 2011|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201054813/http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|url-status=live}}), that the Sun Java design team licensed the Oberon compiler sources a number of years prior to the release of Java and examined it: a (relative) compactness, type safety, garbage collection, no multiple inheritance for classes{{snd}} all these key overall design features are shared by Java and Oberon.</ref> [[Objective-C]],<ref>[[Patrick Naughton]] cites [[Objective-C]] as a strong influence on the design of the Java programming language, stating that notable direct derivatives include Java interfaces (derived from Objective-C's [[Objective-C#Protocols|protocol]]) and primitive wrapper classes. [http://cs.gmu.edu/~sean/stuff/java-objc.html] {{Webarchive|url=https://web.archive.org/web/20110713014816/http://cs.gmu.edu/~sean/stuff/java-objc.html|date=July 13, 2011}}</ref> [[UCSD Pascal]],<ref>{{cite web |url=http://www.fscript.org/prof/javapassport.pdf |quote=The project went ahead under the name ''green'' and the language was based on an old model of [[UCSD Pascal]], which makes it possible to generate interpretive code. |title=History of Java|work=Java Application Servers Report|author=TechMetrix Research|year=1999|archive-url=https://web.archive.org/web/20101229090912/http://www.fscript.org/prof/javapassport.pdf|archive-date=December 29, 2010|url-status=dead}}</ref><ref>{{cite web |title=A Conversation with James Gosling – ACM Queue |date=August 31, 2004 |url=http://queue.acm.org/detail.cfm?id=1017013 |publisher=Queue.acm.org |access-date=2010-06-09|archive-url=https://web.archive.org/web/20150716194245/http://queue.acm.org/detail.cfm?id=1017013|archive-date=July 16, 2015 |url-status=live}}</ref> [[Object Pascal]]<ref>{{cite report |author=((The Java Language Team)) |publisher=JavaSoft, Sun Microsystems, Inc. |url=http://java.sun.com/docs/white/delegates.html |quote=In the summer of 1996, Sun was designing the precursor to what is now the event model of the AWT and the JavaBeans component architecture. Borland contributed greatly to this process. We looked very carefully at Delphi Object Pascal and built a working prototype of bound method references in order to understand their interaction with the Java programming language and its APIs. |archive-url=https://web.archive.org/web/20120627043929/http://java.sun.com/docs/white/delegates.html |archive-date=2012-06-27 |url-status=dead |type=White Paper |title=About Microsoft's "Delegates"}}</ref> | influenced = [[Ada (programming language)|Ada 2005]], [[BeanShell]], [[C Sharp (programming language)|C#]], [[Chapel (programming language)|Chapel]],<ref name="chplspec">{{cite web|title=Chapel spec (Acknowledgements)|url=http://chapel.cray.com/spec/spec-0.98.pdf|date=2015-10-01|access-date=2016-01-14|publisher=Cray Inc.|archive-url=https://web.archive.org/web/20160205114946/http://chapel.cray.com/spec/spec-0.98.pdf|archive-date=February 5, 2016|url-status=live}}</ref> [[Clojure]], [[ECMAScript]], [[Fantom (programming language)|Fantom]], [[Gambas]],<ref name="gambas">{{cite web|url=http://gambaswiki.org/wiki/doc/intro?nh&l=en|title=Gambas Documentation Introduction|publisher=Gambas Website|access-date=2017-10-09|archive-url=https://web.archive.org/web/20171009041815/http://gambaswiki.org/wiki/doc/intro?nh&l=en|archive-date=October 9, 2017|url-status=live}}</ref> [[Groovy (programming language)|Groovy]], [[Hack (programming language)|Hack]],<ref>{{cite magazine|url=http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|title=Facebook Q&A: Hack brings static typing to PHP world|magazine=InfoWorld|date=March 26, 2014|access-date=2015-01-11|archive-url=https://web.archive.org/web/20150213220946/http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|archive-date=February 13, 2015|url-status=live}}</ref> [[Haxe]], [[Visual J Sharp|J#]], [[Kotlin (programming language)|Kotlin]], [[PHP]], [[Python (programming language)|Python]], [[Scala (programming language)|Scala]], [[Seed7]], [[Vala (programming language)|Vala]], [[JavaScript]], [[JS++]], [[ArkTS]] | website = {{ubl|{{URL|oracle.com/java/}}|{{URL|java.com}}|{{URL|dev.java}}}} | file_ext = .java, [[Java class file|.class]], [[JAR (file format)|.jar]], .jmod | wikibooks = Java Programming }} [[File:Duke (Java mascot) waving.svg|thumb|upright=0.5|Duke, the Java mascot]] [[File:James Gosling 2008.jpg|thumb|[[James Gosling]], the creator of Java, in 2008]] '''جاوا''' (Java) هڪ اعليٰ سطحي، ڪلاس تي ٻڌل، مقصد تي مبني پروگرامنگ ٻولي آهي. اها هڪ عام مقصدي پروگرامنگ ٻولي آهي جنهن جو مقصد پروگرامرن کي هڪ ڀيرو لکڻ، ڪٿي به هلائڻ (WORA) جی سھولت ڏيڻ آهي،<ref>{{cite web|url=http://www.computerweekly.com/Articles/2002/05/02/186793/write-once-run-anywhere.htm|title=Write once, run anywhere?|date=May 2, 2002|publisher=[[Computer Weekly]]|archive-url=https://web.archive.org/web/20210813193857/https://www.computerweekly.com/feature/Write-once-run-anywhere|archive-date=August 13, 2021|access-date=2009-07-27|url-status=live}}</ref> مطلب ته مرتب ڪيل جاوا ڪوڊ انهن سڀني پليٽ فارمن تي، بغير ڪنهن کي ٻيهر ٺاهڻ جي، هلائي سگهي ٿو جيڪي جاوا کي سپورٽ ڪن ٿيون. <ref name="design_goals2">{{cite web|url=https://www.oracle.com/technetwork/java/intro-141325.html|title=1.2 Design Goals of the Java Programming Language|date=January 1, 1999|publisher=Oracle|archive-url=https://web.archive.org/web/20130123204103/http://www.oracle.com/technetwork/java/intro-141325.html|archive-date=January 23, 2013|access-date=2013-01-14|url-status=live}}</ref>جاوا ايپليڪيشنون عام طور تي بائيٽ ڪوڊ تي مرتب ٿيل آهن جيڪي ڪنهن به جاوا ورچوئل مشين (JVM) تي هلائي سگهن ٿيون بغير ڪنهن بنيادي ڪمپيوٽر جي فن تعمير جي. جاوا جو نحو C ۽ C++ سان ملندڙ جلندڙ آهي، پر انهن مان ڪنهن به هڪ جي ڀيٽ ۾ گهٽ گهٽ-سطح جون سهولتون آهن. جاوا رن ٽائم متحرڪ صلاحيتون مهيا ڪري ٿو (جهڙوڪ عڪاسي ۽ رن ٽائم ڪوڊ ترميم) جيڪي عام طور تي روايتي مرتب ڪيل ٻولين ۾ موجود نه آهن. جاوا پنهنجي ریليز ٿيڻ کان پوءِ جلدي مقبوليت حاصل ڪئي ۽ ان وقت کان وٺي هڪ تمام مشهور پروگرامنگ ٻولي رهي آهي.<ref>{{Cite web|url=https://github.com/readme/featured/java-programming-language|title=Don't call it a comeback: Why Java is still champ|last=Melanson|first=Mike|date=August 9, 2022|website=[[GitHub]]|archive-url=https://web.archive.org/web/20230825195416/https://github.com/readme/featured/java-programming-language|archive-date=August 25, 2023|access-date=October 15, 2023|url-status=live}}</ref> GitHub جي مطابق سال 2022ع ۾ جاوا ٽيون مقبول ترين پروگرامنگ ٻولي هئي.<ref>{{Cite web|url=https://octoverse.github.com/2022/top-programming-languages|title=The top programming languages|website=The State of the Octoverse|publisher=[[GitHub]]|archive-url=https://web.archive.org/web/20230802203718/https://octoverse.github.com/2022/top-programming-languages|archive-date=2 August 2023|access-date=15 October 2023|url-status=live}}</ref> جيتوڻيڪ اڃا تائين وڏي پيماني تي مشهور آهي، تازو سالن ۾ جاوا جي استعمال ۾ بتدريج گهٽتائي آئي آهي ٻين ٻولين سان گڏ JVM استعمال ڪندي مقبوليت حاصل ڪئي.<ref name=":02">{{cite magazine|last=McMillan|first=Robert|date=August 1, 2013|title=Is Java Losing Its Mojo?|url=https://www.wired.com/2013/01/java-no-longer-a-favorite/|url-access=limited|url-status=live|magazine=[[wired.com|Wired]]|archive-url=https://web.archive.org/web/20170215115409/https://www.wired.com/2013/01/java-no-longer-a-favorite/|archive-date=February 15, 2017|access-date=October 15, 2023|quote=}}</ref> جاوا اصل ۾ جيمز گوسلنگ پاران سن مائڪرو سسٽم ۾ ترقي ڪئي وئي هئي. اهو مئي 1995ع ۾ سن جي جاوا پليٽ فارم جي بنيادي جزو طور جاري ڪيو ويو. اصل ۽ حوالن تي عملدرآمد جاوا ڪمپليرز، ورچوئل مشينون، ۽ ڪلاس لائبرريون اصل ۾ سن پاران مالڪاڻي لائسنس تحت جاري ڪيون ويون. مئي 2007ع تائين، جاوا ڪميونٽي پروسيس جي وضاحتن جي تعميل ۾، سن پنهنجي اڪثر جاوا ٽيڪنالاجيز کي GPL-2.0-صرف لائسنس تحت لائسنس ڏنو هو. Oracle پيش ڪري ٿو پنهنجي HotSpot جاوا ورچوئل مشين، جڏهن ته سرڪاري حوالن تي عمل درآمد OpenJDK JVM آهي جيڪو مفت اوپن سورس سافٽ ويئر آهي ۽ اڪثر ڊولپرز پاران استعمال ڪيو ويندو آهي ۽ تقريبن سڀني لينڪس جي تقسيم لاءِ ڊفالٽ JVM آهي. 2024ع تائين، جاوا 22 جديد نسخو آهي. جاوا 8، 11، 17، ۽ 21 اڳوڻو LTS ورزن آھن اڃا تائين سرڪاري طور تي سپورٽ ٿيل آھن. ==تاريخ== {{Short description|Object-oriented programming language}} {{Distinguish|JavaScript}} {{Redirect|Openframe|the ten-pin bowling term|Open frame}} {{redirect|Java language|the language spoken in Java|Javanese language}} {{Pp-semi-indef|small=yes}} {{Use mdy dates|date=August 2017}} {{Infobox programming language | name = Java | logo = Java programming language logo.svg | logo size = 121px | logo caption = | paradigm = [[Programming paradigm#Multi-paradigm|Multi-paradigm]]: [[generic programming|generic]], [[Object-oriented programming|object-oriented]] ([[class-based programming|class-based]]), [[functional programming|functional]], [[imperative programming|imperative]], [[reflective programming|reflective]], [[concurrent computing|concurrent]] | year = {{Start date and age|1995|5|23}}<ref>{{cite magazine|url=https://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|title=Java's 20 Years of Innovation|magazine=Forbes|date=May 20, 2015|access-date=March 18, 2016|author=Binstock, Andrew|archive-url=https://web.archive.org/web/20160314102242/http://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|archive-date=March 14, 2016|url-status=live}}</ref> | latest release version = {{wikidata|property|preferred|references|edit|Q251|P348}} | latest release date = {{Start date and age|{{wikidata|qualifier|preferred|single|Q251|P348|P577}}}} | designer = [[James Gosling]] | developer = [[Oracle Corporation]] | typing = [[type system|Static, strong, safe]], [[nominal type system|nominative]], [[manifest typing|manifest]] | memory management = [[Garbage collection (computer science)|Garbage-collected]] | influenced_by = [[CLU (programming language)|CLU]],<ref name="BarbaraLiskov">{{cite book |title=Program Development in Java – Abstraction, Specification, and Object-Oriented Design|author=[[Barbara Liskov]] with [[John Guttag]]|isbn=978-0-201-65768-5|publisher=USA, Addison Wesley|year=2000}}</ref> [[Simula67]],<ref name="BarbaraLiskov" /> [[Lisp (programming language)|Lisp]],<ref name="BarbaraLiskov" /> [[Smalltalk]],<ref name="BarbaraLiskov" /> [[Ada (programming language)|Ada 83]], [[C++]],<ref>{{cite web|url=https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133|title=Cracking The Java Programming Interview :: 2000+ Java Interview Que/Ans|first=Harry H.|last=Chaudhary|access-date=2016-05-29|date=2014-07-28|archive-date=September 29, 2023|archive-url=https://web.archive.org/web/20230929040943/https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133#v=onepage&q&f=false|url-status=live}}</ref> [[C Sharp (programming language)|C#]],<ref>Java&nbsp;5.0 added several new language features (the [[foreach loop|enhanced for loop]], [[object type (object-oriented programming)#Autoboxing|autoboxing]], [[variadic function|varargs]] and [[Java annotation|annotations]]), after they were introduced in the similar (and competing) [[C Sharp (programming language)|C#]] language. [http://www.barrycornelius.com/papers/java5/] {{Webarchive|url=https://web.archive.org/web/20110319065438/http://www.barrycornelius.com/papers/java5/|date=March 19, 2011}} [http://www.levenez.com/lang/] {{Webarchive|url=https://web.archive.org/web/20060107162045/http://www.levenez.com/lang/|date=January 7, 2006}}</ref> [[Eiffel (programming language)|Eiffel]],<ref>{{cite web|author1=Gosling, James|author2=McGilton, Henry|title=The Java Language Environment|date=May 1996|url=https://www.oracle.com/technetwork/java/langenv-140151.html|access-date=May 6, 2014|archive-url=https://web.archive.org/web/20140506214653/http://www.oracle.com/technetwork/java/langenv-140151.html|archive-date=May 6, 2014 |url-status=live}}</ref> [[Mesa (programming language)|Mesa]],<ref>{{cite web|author1=Gosling, James|author2=Joy, Bill |author3=Steele, Guy|author4=Bracha, Gilad|title=The Java Language Specification, 2nd Edition |url=https://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|access-date=February 8, 2008|archive-url=https://web.archive.org/web/20110805051057/http://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|archive-date=August 5, 2011 |url-status=live}}</ref> [[Modula-3]],<ref>{{cite web |url=http://www.computerworld.com.au/index.php/id;1422447371;pp;3;fp;4194304;fpid;1|title=The A-Z of Programming Languages: Modula-3 |publisher=Computerworld|access-date=2010-06-09|url-status=dead|archive-url=https://web.archive.org/web/20090105145818/http://www.computerworld.com.au/index.php/id%3B1422447371%3Bpp%3B3%3Bfp%3B4194304%3Bfpid%3B1|archive-date=January 5, 2009}}</ref> [[Oberon (programming language)|Oberon]],<ref>[[Niklaus Wirth]] stated on a number of public occasions, e.g. in a lecture at the Polytechnic Museum, Moscow in September 2005 (several independent first-hand accounts in Russian exist, e.g. one with an audio recording: {{cite web|author=Filippova, Elena|title=Niklaus Wirth's lecture at the Polytechnic Museum in Moscow|date=September 22, 2005|url=http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|access-date=November 20, 2011|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201054813/http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|url-status=live}}), that the Sun Java design team licensed the Oberon compiler sources a number of years prior to the release of Java and examined it: a (relative) compactness, type safety, garbage collection, no multiple inheritance for classes{{snd}} all these key overall design features are shared by Java and Oberon.</ref> [[Objective-C]],<ref>[[Patrick Naughton]] cites [[Objective-C]] as a strong influence on the design of the Java programming language, stating that notable direct derivatives include Java interfaces (derived from Objective-C's [[Objective-C#Protocols|protocol]]) and primitive wrapper classes. [http://cs.gmu.edu/~sean/stuff/java-objc.html] {{Webarchive|url=https://web.archive.org/web/20110713014816/http://cs.gmu.edu/~sean/stuff/java-objc.html|date=July 13, 2011}}</ref> [[UCSD Pascal]],<ref>{{cite web |url=http://www.fscript.org/prof/javapassport.pdf |quote=The project went ahead under the name ''green'' and the language was based on an old model of [[UCSD Pascal]], which makes it possible to generate interpretive code. |title=History of Java|work=Java Application Servers Report|author=TechMetrix Research|year=1999|archive-url=https://web.archive.org/web/20101229090912/http://www.fscript.org/prof/javapassport.pdf|archive-date=December 29, 2010|url-status=dead}}</ref><ref>{{cite magazine |title=A Conversation with James Gosling |magazine=[[ACM Queue]] |date=August 31, 2004 |url=http://queue.acm.org/detail.cfm?id=1017013 |publisher=[[Association for Computing Machinery]] |volume=2 |issue=5 |access-date=2010-06-09|archive-url=https://web.archive.org/web/20150716194245/http://queue.acm.org/detail.cfm?id=1017013|archive-date=July 16, 2015 |url-status=live}}</ref> [[Object Pascal]]<ref>{{cite report |author=((The Java Language Team)) |publisher=JavaSoft, Sun Microsystems, Inc. |url=http://java.sun.com/docs/white/delegates.html |quote=In the summer of 1996, Sun was designing the precursor to what is now the event model of the AWT and the JavaBeans component architecture. Borland contributed greatly to this process. We looked very carefully at Delphi Object Pascal and built a working prototype of bound method references in order to understand their interaction with the Java programming language and its APIs. |archive-url=https://web.archive.org/web/20120627043929/http://java.sun.com/docs/white/delegates.html |archive-date=2012-06-27 |url-status=dead |type=White Paper |title=About Microsoft's 'Delegates'}}</ref> | influenced = [[Ada (programming language)|Ada 2005]], [[ArkTS]], [[BeanShell]], [[C Sharp (programming language)|C#]], [[Chapel (programming language)|Chapel]],<ref name="chplspec">{{cite web|title=Chapel spec (Acknowledgements)|url=http://chapel.cray.com/spec/spec-0.98.pdf|date=2015-10-01|access-date=2016-01-14|publisher=Cray Inc.|archive-url=https://web.archive.org/web/20160205114946/http://chapel.cray.com/spec/spec-0.98.pdf|archive-date=February 5, 2016|url-status=live}}</ref> [[Clojure]], [[ECMAScript]], [[Fantom (programming language)|Fantom]], [[Gambas]],<ref name="gambas">{{cite web|url=http://gambaswiki.org/wiki/doc/intro?nh&l=en|title=Gambas Documentation Introduction|publisher=Gambas Website|access-date=2017-10-09|archive-url=https://web.archive.org/web/20171009041815/http://gambaswiki.org/wiki/doc/intro?nh&l=en|archive-date=October 9, 2017|url-status=live}}</ref> [[Apache Groovy|Groovy]], [[Hack (programming language)|Hack]],<ref>{{cite magazine|url=http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|title=Facebook Q&A: Hack brings static typing to PHP world|magazine=InfoWorld|date=March 26, 2014|access-date=2015-01-11|archive-url=https://web.archive.org/web/20150213220946/http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|archive-date=February 13, 2015|url-status=live}}</ref> [[Haxe]], [[Visual J Sharp|J#]], [[JavaScript]], [[JS++]], [[Kotlin]], [[PHP]], [[Python (programming language)|Python]], [[Scala (programming language)|Scala]], [[Vala (programming language)|Vala]] | website = {{ubl|{{URL|oracle.com/java/}}|{{URL|java.com}}|{{URL|dev.java}}}} | file_ext = .java, [[Java class file|.class]], [[JAR (file format)|.jar]], .jmod, [[WAR (file format)|.war]] | wikibooks = Java Programming }} {{Java sidebar}} '''Java''' is a [[High-level programming language|high-level]], [[General-purpose programming language|general-purpose]], [[Memory safety|memory-safe]], [[object-oriented programming|object-oriented]] [[programming language]]. It is intended to let [[programmer]]s ''write once, run anywhere'' ([[Write once, run anywhere|WORA]]),<ref>{{cite web|title=Write once, run anywhere?|date=May 2, 2002 |publisher=[[Computer Weekly]] |url=http://www.computerweekly.com/Articles/2002/05/02/186793/write-once-run-anywhere.htm|access-date=2009-07-27|url-status=live|archive-date=August 13, 2021|archive-url=https://web.archive.org/web/20210813193857/https://www.computerweekly.com/feature/Write-once-run-anywhere}}</ref> meaning that [[compiler|compiled]] Java code can run on all platforms that support Java without the need to recompile.<ref name="design_goals">{{cite web |title=1.2 Design Goals of the Java Programming Language|date=January 1, 1999 |url=https://www.oracle.com/technetwork/java/intro-141325.html|access-date=2013-01-14|publisher=Oracle|archive-url=https://web.archive.org/web/20130123204103/http://www.oracle.com/technetwork/java/intro-141325.html|archive-date=January 23, 2013|url-status=live}}</ref> Java applications are typically compiled to [[Java bytecode|bytecode]] that can run on any [[Java virtual machine]] (JVM) regardless of the underlying [[computer architecture]]. The [[syntax (programming languages)|syntax]] of Java is similar to [[C (programming language)|C]] and [[C++]], but has fewer [[low-level programming language|low-level]] facilities than either of them. The Java runtime provides dynamic capabilities (such as [[Reflective programming|reflection]] and runtime code modification) that are typically not available in traditional compiled languages. Java gained popularity shortly after its release, and has been a popular programming language since then.<ref>{{Cite web |last=Melanson |first=Mike |date=August 9, 2022 |title=Don't call it a comeback: Why Java is still champ |url=https://github.com/readme/featured/java-programming-language |url-status=live |archive-url=https://web.archive.org/web/20230825195416/https://github.com/readme/featured/java-programming-language |archive-date=August 25, 2023 |access-date=October 15, 2023 |website=[[GitHub]]}}</ref> Java was the third most popular programming language in {{As of|2022|bare=yes}} according to [[GitHub]].<ref>{{Cite web |title=The top programming languages |url=https://octoverse.github.com/2022/top-programming-languages |url-status=live |archive-url=https://web.archive.org/web/20230802203718/https://octoverse.github.com/2022/top-programming-languages |archive-date=2 August 2023 |access-date=15 October 2023 |website=The State of the Octoverse |publisher=[[GitHub]]}}</ref> Although still widely popular, there has been a gradual decline in use of Java in recent years with [[List of JVM languages|other languages using JVM]] gaining popularity.<ref name=":0">{{cite magazine |last=McMillan |first=Robert |date=August 1, 2013 |title=Is Java Losing Its Mojo? |url=https://www.wired.com/2013/01/java-no-longer-a-favorite/ |url-access=limited |url-status=live |magazine=[[wired.com|Wired]] |archive-url=https://web.archive.org/web/20170215115409/https://www.wired.com/2013/01/java-no-longer-a-favorite/ |archive-date=February 15, 2017 |access-date=October 15, 2023 |quote=}}</ref> Java was designed by [[James Gosling]] at [[Sun Microsystems]]. It was released in May 1995 as a core component of Sun's [[Java (software platform)|Java platform]]. The original and [[reference implementation]] Java [[compiler]]s, virtual machines, and [[library (computing)|class libraries]] were released by Sun under [[proprietary license]]s. As of May 2007, in compliance with the specifications of the [[Java Community Process]], Sun had [[Software relicensing|relicensed]] most of its Java technologies under the [[GNU General Public License|GPL-2.0-only]] license. [[Oracle Corporation|Oracle]], which bought Sun in 2010, offers its own [[HotSpot]] Java virtual machine. However, the official [[reference implementation]] is the [[OpenJDK]] JVM, which is open-source software used by most developers and is the default JVM for almost all [[Linux distribution]]s. [[Java version history|Java 26]] is the current version {{as of|lc=y|2026|March}}. Java 25 is [[long-term support]] (LTS) version still under maintenance by Oracle (as [[permissive license|permissively licensed]]); Java 21 is also still an LTS version though users "wanting to continue with permissively licensed versions of Java after September of 2026 should upgrade to Oracle JDK 25 or later"<ref>{{Cite web |title=Oracle Java SE Support Roadmap |url=https://www.oracle.com/java/technologies/java-se-support-roadmap.html |access-date=2026-04-12 |website=www.oracle.com |language=en-US}}</ref> according to Oracle. Oracle also provides proprietary "Java SE OTN license" for it (for longer) and Java 21 LTS, 11 LTS and 8 LTS. Note, Oracle still supports Java 8 LTS at no cost (but with a [[proprietary license]]) for ''personal'' use. Others also support same LTS versions (commercially), and latest, and some even down to Java 6 and 7 (to 2027 or March 2028 depending). ==ايڊيشن== ==عملدرآمد سسٽم== ==نحو== ==خاص ڪلاس== ==تنقيد== ==ڪلاس لائبريريون== ==دستاويزون== ==عملدرآمد== ==جاوا پليٽ فارم کان ٻاهر استعمال== جاوا پروگرامنگ ٻولي کي سافٽ ويئر پليٽ فارم جي موجودگي جي ضرورت آهي ترتيب ڏنل پروگرامن تي عمل ڪرڻ لاء. اوريڪل (Oracle) جاوا سان استعمال ڪرڻ لاءِ جاوا پليٽ فارم فراهم ڪري ٿو. اینڊروئڊ ایس ڊي ڪي (Android SDK) هڪ متبادل سافٽ ويئر پليٽ فارم آهي، جيڪو بنيادي طور تي پنهنجي جي یو آء (GUI) سسٽم سان اینڊروئڊ ايپليڪيشنون ٺاهڻ لاءِ استعمال ڪيو ويندو آهي. ===اینڊروئڊ=== جاوا ٻولي اینڊروئڊ، هڪ کليل ذريعو موبائل آپريٽنگ سسٽم، ۾ هڪ اهم ستون آهي. جيتوڻيڪ اینڊروئڊ، لینوڪس ڪرنیل (Linux kernel) تي ٺهيل آهي، گهڻو ڪري "C" بولی ۾ لکيو ويو آهي، اینڊروئڊ ایس ڊي ڪي، اینڊروئڊ ايپليڪيشنن لاءِ بنياد طور جاوا ٻولي استعمال ڪري ٿو پر ان جي معياري جي.یو.آء (GUI)، ایس.اي. (SE)، ایم.اي. (ME) يا ٻيون قائم ڪيل جاوا معيار استعمال نٿو ڪري. اینڊروئڊ ایس.ڊي.ڪي. پاران سپورٽ ڪيل بائٽ ڪوڊ ٻولي (bytecode language) جاوا بائٽ ڪوڊ سان مطابقت نه رکي ٿي ۽ پنھنجي ورچوئل مشين تي ھلندي آھي، گھٽ ميموري ڊيوائسز جھڙوڪ اسمارٽ فونز ۽ ٽيبليٽ ڪمپيوٽرن لاءِ بھتر آھي. اینڊروئڊ ورزن تي مدار رکندي، بائيٽ ڪوڊ يا ته ڊالڪ ورچوئل مشين جي ذريعي تفسير ڪيو ويو آهي يا اینڊروئڊ رن ٽائم پاران اصلي ڪوڊ ۾ مرتب ڪيو ويو آهي. اینڊروئڊ مڪمل جاوا ایس.اي. معياري لائبريري مهيا نٿو ڪري، جيتوڻيڪ اینڊروئڊ ایس.ڊي.ڪي. ۾ ان جي وڏي سب سیٽ جو هڪ آزاد عمل شامل آهي. اهو جاوا 6 ۽ ڪجهه جاوا 7 خاصيتن کي سپورٽ ڪري ٿو، معياري لائبريري (Apache Harmony) سان مطابقت رکندڙ عمل درآمد پيش ڪري ٿو. ===تڪرار=== گوگل انڪارپوریشن، اینڊروئڊ ۾ جاوا سان لاڳاپيل ٽيڪنالاجي جو استعمال اوريڪل انڪارپوریشن ۽ گوگل انڪارپوریشن جي وچ ۾ قانوني تڪرار جو سبب بڻيو. 7 مئي 2012ع تي، هڪ سان فرانسسڪو جيوري معلوم ڪيو ته جيڪڏهن اي.پي.آء (APIs) ڪاپي رائيٽ ٿي سگهي ٿي، ته پوءِ گوگل اینڊروئڊ ڊیوائيسز ۾ جاوا جي استعمال سان اوريڪل جي ڪاپي رائيٽ جي خلاف ورزي ڪئي هئي. ضلعي جج وليم السپ 31 مئي، 2012ع تي فيصلو ڏنو ته اي.پي.آء ڪاپي رائيٽ نٿا ٿي سگهن، پر مئي، 2014ع ۾ آمريڪي عدالت آف اپيلز فار فيڊرل سرڪٽ طرفان ان کي رد ڪيو ويو. 26 مئي، 2016ع تي، ضلعي عدالت گوگل جي حق ۾ فيصلو ڏنو. اینڊروئڊ ۾ جاوا اي.پي.آء جي ڪاپي رائيٽ جي خلاف ورزي جي حڪمراني منصفانه استعمال کي قائم ڪري ٿي. مارچ 2018ع ۾، هي حڪمران اپيل ڪورٽ طرفان رد ڪيو ويو، جنهن سان فرانسسڪو ۾ وفاقي عدالت کي نقصان جي تعين ڪرڻ جو ڪيس موڪليو ويو. گوگل جنوري 2019ع ۾ آمريڪا جي سپريم ڪورٽ ۾ سرٽيوريري جي رٽ لاءِ هڪ درخواست داخل ڪئي ته انهن ٻن حڪمن کي چيلينج ڪرڻ لاءِ جيڪي اپيل ڪورٽ طرفان اوريڪل جي حق ۾ ڪيا ويا. 5 اپريل، 2021ع تي، عدالت گوگل جي حق ۾ 6-2 جو فيصلو ڪيو، ته جاوا اي.پي.آء جي استعمال کي مناسب استعمال سمجهيو وڃي. تنهن هوندي، عدالت اي.پي.آء جي ڪاپي رائيٽ تي حڪمراني ڪرڻ کان انڪار ڪري ڇڏيو، ان جي بدران چونڊ ڪري انهن جي حڪمراني جو تعين ڪرڻ لاءِ، "خالص دليل جي خاطر" جاوا جي اي.پي.آء. ڪاپي رائيٽ قابل غور ڪندي. ==پڻ ڏسو== {{Portal|ڪمپيوٽر پروگرامنگ}} * سي شارپ (#C) پروگرامنگ جي ٻولي * سي ++ (++C) * جاوا APIs جي فهرست * جاوا فريم ورڪ جي فهرست * JVM ٻولين جي فهرست * جاوا ورچوئل مشينن جي فهرست * سي شارپ ۽ جاوا جو موازنو * جاوا ۽ C++ جو موازنو * پروگرامنگ ٻولين جو موازنو ==حوالا== {{حوالا}} ==خارجي لنڪس== * * {{Commons-inline}} * {{Wikibooks-inline|Java Programming}} * [https://discu.eu/weekly/java/ ''Java Weekly''] {{Webarchive|url=https://web.archive.org/web/20240822213928/https://discu.eu/weekly/java/ |date=2024-08-22 }} {{Authority control}} [[زمرو:جاوا (پروگرامنگ ٻولي)|جاوا]] [[زمرو:پروگرامنگ ٻوليون]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر ٻوليون]] [[زمرو:سن مائڪرو سسٽم]] [[زمرو:JVM پروگرامنگ ٻوليون]] [[زمرو:سي پروگرامنگ ٻولي خاندان]] [[زمرو:سي پروگرامنگ ٻولي]] [[زمرو:مرتب ڪيل پروگرامنگ ٻوليون]] [[زمرو:ڪلاس تي ٻڌل پروگرامنگ ٻوليون]] [[زمرو:هم آهنگ پروگرامنگ ٻوليون]] [[زمرو:ملٽي پيراڊائم پروگرامنگ ٻوليون]] [[زمرو:جاوا پليٽ فارم|پروگرامنگ ٻولي]] [[زمرو:1995 ۾ ٺاهيل پروگرامنگ ٻوليون]] [[زمرو:مضمون مثال طور جاوا ڪوڊ]] [[زمرو:جاوا وضاحت جي درخواستون|پروگرامنگ ٻولي]] [[زمرو:جامد ٽائيپ ٿيل پروگرامنگ ٻوليون]] [[زمرو:اعتراض تي مبني پروگرامنگ ٻوليون]] dvfu6kxhmawoaf3yqrtd37e3dcayafw 371873 371872 2026-04-17T11:36:05Z Ibne maryam 17680 371873 wikitext text/x-wiki {{Short description|Object-oriented programming language}} {{Distinguish|Java (software platform)|JavaScript|Java |Javanese language}} {{Infobox language | name = Java | logo = Java programming language logo.svg | logo size = 121px | logo caption = | paradigm = [[Programming paradigm#Multi-paradigm|Multi-paradigm]]: [[generic programming|generic]], [[object-oriented]] ([[class-based programming|class-based]]), [[functional programming|functional]], [[imperative programming|imperative]], [[reflection (computer programming)|reflective]], [[concurrent computing|concurrent]] | year = {{Start date and age|1995|5|23}}<ref>{{cite magazine|url=https://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|title=Java's 20 Years of Innovation|magazine=Forbes|date=May 20, 2015|access-date=March 18, 2016|author=Binstock, Andrew|archive-url=https://web.archive.org/web/20160314102242/http://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|archive-date=March 14, 2016|url-status=live}}</ref> | discontinued = <!-- Set to yes if software is discontinued, otherwise omit. --> | ver layout = <!-- simple (default) or stacked --> | latest release version = {{wikidata|property|edit|reference|P548=Q2804309|P348}} | latest release date = {{start date and age|{{wikidata|qualifier|single|P548=Q2804309|P348|P577}}}} | designer = [[James Gosling]] | developer = [[Oracle Corporation]] | typing = [[type system|Static, strong, safe]], [[nominal type system|nominative]], [[manifest typing|manifest]] | memory management = [[Garbage collection (computer science)|Automatic garbage collection]] | influenced_by = [[CLU (programming language)|CLU]],<ref name="BarbaraLiskov">{{cite book |title=Program Development in Java - Abstraction, Specification, and Object-Oriented Design|author=[[Barbara Liskov]] with [[John Guttag]]|isbn=9780201657685|publisher=USA, Addison Wesley|year=2000}}</ref> [[Simula67]],<ref name="BarbaraLiskov"/> [[Lisp (programming language)|Lisp]],<ref name="BarbaraLiskov"/> [[Smalltalk]],<ref name="BarbaraLiskov"/> [[Ada (programming language)|Ada 83]], [[C++]],<ref>{{cite web|url=https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133|title=Cracking The Java Programming Interview :: 2000+ Java Interview Que/Ans|first=Harry H.|last=Chaudhary|access-date=2016-05-29|date=2014-07-28|archive-date=September 29, 2023|archive-url=https://web.archive.org/web/20230929040943/https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133#v=onepage&q&f=false|url-status=live}}</ref> [[C Sharp (programming language)|C#]],<ref>Java&nbsp;5.0 added several new language features (the [[foreach loop|enhanced for loop]], [[object type (object-oriented programming)#Autoboxing|autoboxing]], [[variadic function|varargs]] and [[Java annotation|annotations]]), after they were introduced in the similar (and competing) [[C Sharp (programming language)|C#]] language. [http://www.barrycornelius.com/papers/java5/] {{Webarchive|url=https://web.archive.org/web/20110319065438/http://www.barrycornelius.com/papers/java5/|date=March 19, 2011}} [http://www.levenez.com/lang/] {{Webarchive|url=https://web.archive.org/web/20060107162045/http://www.levenez.com/lang/|date=January 7, 2006}}</ref> [[Eiffel (programming language)|Eiffel]],<ref>{{cite web|author1=Gosling, James|author2=McGilton, Henry|title=The Java Language Environment|date=May 1996|url=https://www.oracle.com/technetwork/java/langenv-140151.html|access-date=May 6, 2014|archive-url=https://web.archive.org/web/20140506214653/http://www.oracle.com/technetwork/java/langenv-140151.html|archive-date=May 6, 2014 |url-status=live}}</ref> [[Mesa (programming language)|Mesa]],<ref>{{cite web|author1=Gosling, James|author2=Joy, Bill |author3=Steele, Guy|author4=Bracha, Gilad|title=The Java Language Specification, 2nd Edition |url=https://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|access-date=February 8, 2008|archive-url=https://web.archive.org/web/20110805051057/http://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|archive-date=August 5, 2011 |url-status=live}}</ref> [[Modula-3]],<ref>{{cite web |url=http://www.computerworld.com.au/index.php/id;1422447371;pp;3;fp;4194304;fpid;1|title=The A-Z of Programming Languages: Modula-3 |publisher=Computerworld|access-date=2010-06-09|url-status=dead|archive-url=https://web.archive.org/web/20090105145818/http://www.computerworld.com.au/index.php/id%3B1422447371%3Bpp%3B3%3Bfp%3B4194304%3Bfpid%3B1|archive-date=January 5, 2009}}</ref> [[Oberon (programming language)|Oberon]],<ref>[[Niklaus Wirth]] stated on a number of public occasions, e.g. in a lecture at the Polytechnic Museum, Moscow in September 2005 (several independent first-hand accounts in Russian exist, e.g. one with an audio recording: {{cite web|author=Filippova, Elena|title=Niklaus Wirth's lecture at the Polytechnic Museum in Moscow|date=September 22, 2005|url=http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|access-date=November 20, 2011|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201054813/http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|url-status=live}}), that the Sun Java design team licensed the Oberon compiler sources a number of years prior to the release of Java and examined it: a (relative) compactness, type safety, garbage collection, no multiple inheritance for classes{{snd}} all these key overall design features are shared by Java and Oberon.</ref> [[Objective-C]],<ref>[[Patrick Naughton]] cites [[Objective-C]] as a strong influence on the design of the Java programming language, stating that notable direct derivatives include Java interfaces (derived from Objective-C's [[Objective-C#Protocols|protocol]]) and primitive wrapper classes. [http://cs.gmu.edu/~sean/stuff/java-objc.html] {{Webarchive|url=https://web.archive.org/web/20110713014816/http://cs.gmu.edu/~sean/stuff/java-objc.html|date=July 13, 2011}}</ref> [[UCSD Pascal]],<ref>{{cite web |url=http://www.fscript.org/prof/javapassport.pdf |quote=The project went ahead under the name ''green'' and the language was based on an old model of [[UCSD Pascal]], which makes it possible to generate interpretive code. |title=History of Java|work=Java Application Servers Report|author=TechMetrix Research|year=1999|archive-url=https://web.archive.org/web/20101229090912/http://www.fscript.org/prof/javapassport.pdf|archive-date=December 29, 2010|url-status=dead}}</ref><ref>{{cite web |title=A Conversation with James Gosling – ACM Queue |date=August 31, 2004 |url=http://queue.acm.org/detail.cfm?id=1017013 |publisher=Queue.acm.org |access-date=2010-06-09|archive-url=https://web.archive.org/web/20150716194245/http://queue.acm.org/detail.cfm?id=1017013|archive-date=July 16, 2015 |url-status=live}}</ref> [[Object Pascal]]<ref>{{cite report |author=((The Java Language Team)) |publisher=JavaSoft, Sun Microsystems, Inc. |url=http://java.sun.com/docs/white/delegates.html |quote=In the summer of 1996, Sun was designing the precursor to what is now the event model of the AWT and the JavaBeans component architecture. Borland contributed greatly to this process. We looked very carefully at Delphi Object Pascal and built a working prototype of bound method references in order to understand their interaction with the Java programming language and its APIs. |archive-url=https://web.archive.org/web/20120627043929/http://java.sun.com/docs/white/delegates.html |archive-date=2012-06-27 |url-status=dead |type=White Paper |title=About Microsoft's "Delegates"}}</ref> | influenced = [[Ada (programming language)|Ada 2005]], [[BeanShell]], [[C Sharp (programming language)|C#]], [[Chapel (programming language)|Chapel]],<ref name="chplspec">{{cite web|title=Chapel spec (Acknowledgements)|url=http://chapel.cray.com/spec/spec-0.98.pdf|date=2015-10-01|access-date=2016-01-14|publisher=Cray Inc.|archive-url=https://web.archive.org/web/20160205114946/http://chapel.cray.com/spec/spec-0.98.pdf|archive-date=February 5, 2016|url-status=live}}</ref> [[Clojure]], [[ECMAScript]], [[Fantom (programming language)|Fantom]], [[Gambas]],<ref name="gambas">{{cite web|url=http://gambaswiki.org/wiki/doc/intro?nh&l=en|title=Gambas Documentation Introduction|publisher=Gambas Website|access-date=2017-10-09|archive-url=https://web.archive.org/web/20171009041815/http://gambaswiki.org/wiki/doc/intro?nh&l=en|archive-date=October 9, 2017|url-status=live}}</ref> [[Groovy (programming language)|Groovy]], [[Hack (programming language)|Hack]],<ref>{{cite magazine|url=http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|title=Facebook Q&A: Hack brings static typing to PHP world|magazine=InfoWorld|date=March 26, 2014|access-date=2015-01-11|archive-url=https://web.archive.org/web/20150213220946/http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|archive-date=February 13, 2015|url-status=live}}</ref> [[Haxe]], [[Visual J Sharp|J#]], [[Kotlin (programming language)|Kotlin]], [[PHP]], [[Python (programming language)|Python]], [[Scala (programming language)|Scala]], [[Seed7]], [[Vala (programming language)|Vala]], [[JavaScript]], [[JS++]], [[ArkTS]] | website = {{ubl|{{URL|oracle.com/java/}}|{{URL|java.com}}|{{URL|dev.java}}}} | file_ext = .java, [[Java class file|.class]], [[JAR (file format)|.jar]], .jmod | wikibooks = Java Programming }} [[File:Duke (Java mascot) waving.svg|thumb|upright=0.5|Duke, the Java mascot]] [[File:James Gosling 2008.jpg|thumb|[[James Gosling]], the creator of Java, in 2008]] '''جاوا''' (Java) هڪ اعليٰ سطحي، ڪلاس تي ٻڌل، مقصد تي مبني پروگرامنگ ٻولي آهي. اها هڪ عام مقصدي پروگرامنگ ٻولي آهي جنهن جو مقصد پروگرامرن کي هڪ ڀيرو لکڻ، ڪٿي به هلائڻ (WORA) جی سھولت ڏيڻ آهي،<ref>{{cite web|url=http://www.computerweekly.com/Articles/2002/05/02/186793/write-once-run-anywhere.htm|title=Write once, run anywhere?|date=May 2, 2002|publisher=[[Computer Weekly]]|archive-url=https://web.archive.org/web/20210813193857/https://www.computerweekly.com/feature/Write-once-run-anywhere|archive-date=August 13, 2021|access-date=2009-07-27|url-status=live}}</ref> مطلب ته مرتب ڪيل جاوا ڪوڊ انهن سڀني پليٽ فارمن تي، بغير ڪنهن کي ٻيهر ٺاهڻ جي، هلائي سگهي ٿو جيڪي جاوا کي سپورٽ ڪن ٿيون. <ref name="design_goals2">{{cite web|url=https://www.oracle.com/technetwork/java/intro-141325.html|title=1.2 Design Goals of the Java Programming Language|date=January 1, 1999|publisher=Oracle|archive-url=https://web.archive.org/web/20130123204103/http://www.oracle.com/technetwork/java/intro-141325.html|archive-date=January 23, 2013|access-date=2013-01-14|url-status=live}}</ref>جاوا ايپليڪيشنون عام طور تي بائيٽ ڪوڊ تي مرتب ٿيل آهن جيڪي ڪنهن به جاوا ورچوئل مشين (JVM) تي هلائي سگهن ٿيون بغير ڪنهن بنيادي ڪمپيوٽر جي فن تعمير جي. جاوا جو نحو C ۽ C++ سان ملندڙ جلندڙ آهي، پر انهن مان ڪنهن به هڪ جي ڀيٽ ۾ گهٽ گهٽ-سطح جون سهولتون آهن. جاوا رن ٽائم متحرڪ صلاحيتون مهيا ڪري ٿو (جهڙوڪ عڪاسي ۽ رن ٽائم ڪوڊ ترميم) جيڪي عام طور تي روايتي مرتب ڪيل ٻولين ۾ موجود نه آهن. جاوا پنهنجي ریليز ٿيڻ کان پوءِ جلدي مقبوليت حاصل ڪئي ۽ ان وقت کان وٺي هڪ تمام مشهور پروگرامنگ ٻولي رهي آهي.<ref>{{Cite web|url=https://github.com/readme/featured/java-programming-language|title=Don't call it a comeback: Why Java is still champ|last=Melanson|first=Mike|date=August 9, 2022|website=[[GitHub]]|archive-url=https://web.archive.org/web/20230825195416/https://github.com/readme/featured/java-programming-language|archive-date=August 25, 2023|access-date=October 15, 2023|url-status=live}}</ref> GitHub جي مطابق سال 2022ع ۾ جاوا ٽيون مقبول ترين پروگرامنگ ٻولي هئي.<ref>{{Cite web|url=https://octoverse.github.com/2022/top-programming-languages|title=The top programming languages|website=The State of the Octoverse|publisher=[[GitHub]]|archive-url=https://web.archive.org/web/20230802203718/https://octoverse.github.com/2022/top-programming-languages|archive-date=2 August 2023|access-date=15 October 2023|url-status=live}}</ref> جيتوڻيڪ اڃا تائين وڏي پيماني تي مشهور آهي، تازو سالن ۾ جاوا جي استعمال ۾ بتدريج گهٽتائي آئي آهي ٻين ٻولين سان گڏ JVM استعمال ڪندي مقبوليت حاصل ڪئي.<ref name=":02">{{cite magazine|last=McMillan|first=Robert|date=August 1, 2013|title=Is Java Losing Its Mojo?|url=https://www.wired.com/2013/01/java-no-longer-a-favorite/|url-access=limited|url-status=live|magazine=[[wired.com|Wired]]|archive-url=https://web.archive.org/web/20170215115409/https://www.wired.com/2013/01/java-no-longer-a-favorite/|archive-date=February 15, 2017|access-date=October 15, 2023|quote=}}</ref> جاوا اصل ۾ جيمز گوسلنگ پاران سن مائڪرو سسٽم ۾ ترقي ڪئي وئي هئي. اهو مئي 1995ع ۾ سن جي جاوا پليٽ فارم جي بنيادي جزو طور جاري ڪيو ويو. اصل ۽ حوالن تي عملدرآمد جاوا ڪمپليرز، ورچوئل مشينون، ۽ ڪلاس لائبرريون اصل ۾ سن پاران مالڪاڻي لائسنس تحت جاري ڪيون ويون. مئي 2007ع تائين، جاوا ڪميونٽي پروسيس جي وضاحتن جي تعميل ۾، سن پنهنجي اڪثر جاوا ٽيڪنالاجيز کي GPL-2.0-صرف لائسنس تحت لائسنس ڏنو هو. Oracle پيش ڪري ٿو پنهنجي HotSpot جاوا ورچوئل مشين، جڏهن ته سرڪاري حوالن تي عمل درآمد OpenJDK JVM آهي جيڪو مفت اوپن سورس سافٽ ويئر آهي ۽ اڪثر ڊولپرز پاران استعمال ڪيو ويندو آهي ۽ تقريبن سڀني لينڪس جي تقسيم لاءِ ڊفالٽ JVM آهي. 2024ع تائين، جاوا 22 جديد نسخو آهي. جاوا 8، 11، 17، ۽ 21 اڳوڻو LTS ورزن آھن اڃا تائين سرڪاري طور تي سپورٽ ٿيل آھن. ==تاريخ== {{Short description|Object-oriented programming language}} {{Distinguish|JavaScript}} {{Infobox language | name = Java | logo = Java programming language logo.svg | logo size = 121px | logo caption = | paradigm = [[Programming paradigm#Multi-paradigm|Multi-paradigm]]: [[generic programming|generic]], [[Object-oriented programming|object-oriented]] ([[class-based programming|class-based]]), [[functional programming|functional]], [[imperative programming|imperative]], [[reflective programming|reflective]], [[concurrent computing|concurrent]] | year = {{Start date and age|1995|5|23}}<ref>{{cite magazine|url=https://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|title=Java's 20 Years of Innovation|magazine=Forbes|date=May 20, 2015|access-date=March 18, 2016|author=Binstock, Andrew|archive-url=https://web.archive.org/web/20160314102242/http://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|archive-date=March 14, 2016|url-status=live}}</ref> | latest release version = {{wikidata|property|preferred|references|edit|Q251|P348}} | latest release date = {{Start date and age|{{wikidata|qualifier|preferred|single|Q251|P348|P577}}}} | designer = [[James Gosling]] | developer = [[Oracle Corporation]] | typing = [[type system|Static, strong, safe]], [[nominal type system|nominative]], [[manifest typing|manifest]] | memory management = [[Garbage collection (computer science)|Garbage-collected]] | influenced_by = [[CLU (programming language)|CLU]],<ref name="BarbaraLiskov">{{cite book |title=Program Development in Java – Abstraction, Specification, and Object-Oriented Design|author=[[Barbara Liskov]] with [[John Guttag]]|isbn=978-0-201-65768-5|publisher=USA, Addison Wesley|year=2000}}</ref> [[Simula67]],<ref name="BarbaraLiskov" /> [[Lisp (programming language)|Lisp]],<ref name="BarbaraLiskov" /> [[Smalltalk]],<ref name="BarbaraLiskov" /> [[Ada (programming language)|Ada 83]], [[C++]],<ref>{{cite web|url=https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133|title=Cracking The Java Programming Interview :: 2000+ Java Interview Que/Ans|first=Harry H.|last=Chaudhary|access-date=2016-05-29|date=2014-07-28|archive-date=September 29, 2023|archive-url=https://web.archive.org/web/20230929040943/https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133#v=onepage&q&f=false|url-status=live}}</ref> [[C Sharp (programming language)|C#]],<ref>Java&nbsp;5.0 added several new language features (the [[foreach loop|enhanced for loop]], [[object type (object-oriented programming)#Autoboxing|autoboxing]], [[variadic function|varargs]] and [[Java annotation|annotations]]), after they were introduced in the similar (and competing) [[C Sharp (programming language)|C#]] language. [http://www.barrycornelius.com/papers/java5/] {{Webarchive|url=https://web.archive.org/web/20110319065438/http://www.barrycornelius.com/papers/java5/|date=March 19, 2011}} [http://www.levenez.com/lang/] {{Webarchive|url=https://web.archive.org/web/20060107162045/http://www.levenez.com/lang/|date=January 7, 2006}}</ref> [[Eiffel (programming language)|Eiffel]],<ref>{{cite web|author1=Gosling, James|author2=McGilton, Henry|title=The Java Language Environment|date=May 1996|url=https://www.oracle.com/technetwork/java/langenv-140151.html|access-date=May 6, 2014|archive-url=https://web.archive.org/web/20140506214653/http://www.oracle.com/technetwork/java/langenv-140151.html|archive-date=May 6, 2014 |url-status=live}}</ref> [[Mesa (programming language)|Mesa]],<ref>{{cite web|author1=Gosling, James|author2=Joy, Bill |author3=Steele, Guy|author4=Bracha, Gilad|title=The Java Language Specification, 2nd Edition |url=https://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|access-date=February 8, 2008|archive-url=https://web.archive.org/web/20110805051057/http://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|archive-date=August 5, 2011 |url-status=live}}</ref> [[Modula-3]],<ref>{{cite web |url=http://www.computerworld.com.au/index.php/id;1422447371;pp;3;fp;4194304;fpid;1|title=The A-Z of Programming Languages: Modula-3 |publisher=Computerworld|access-date=2010-06-09|url-status=dead|archive-url=https://web.archive.org/web/20090105145818/http://www.computerworld.com.au/index.php/id%3B1422447371%3Bpp%3B3%3Bfp%3B4194304%3Bfpid%3B1|archive-date=January 5, 2009}}</ref> [[Oberon (programming language)|Oberon]],<ref>[[Niklaus Wirth]] stated on a number of public occasions, e.g. in a lecture at the Polytechnic Museum, Moscow in September 2005 (several independent first-hand accounts in Russian exist, e.g. one with an audio recording: {{cite web|author=Filippova, Elena|title=Niklaus Wirth's lecture at the Polytechnic Museum in Moscow|date=September 22, 2005|url=http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|access-date=November 20, 2011|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201054813/http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|url-status=live}}), that the Sun Java design team licensed the Oberon compiler sources a number of years prior to the release of Java and examined it: a (relative) compactness, type safety, garbage collection, no multiple inheritance for classes{{snd}} all these key overall design features are shared by Java and Oberon.</ref> [[Objective-C]],<ref>[[Patrick Naughton]] cites [[Objective-C]] as a strong influence on the design of the Java programming language, stating that notable direct derivatives include Java interfaces (derived from Objective-C's [[Objective-C#Protocols|protocol]]) and primitive wrapper classes. [http://cs.gmu.edu/~sean/stuff/java-objc.html] {{Webarchive|url=https://web.archive.org/web/20110713014816/http://cs.gmu.edu/~sean/stuff/java-objc.html|date=July 13, 2011}}</ref> [[UCSD Pascal]],<ref>{{cite web |url=http://www.fscript.org/prof/javapassport.pdf |quote=The project went ahead under the name ''green'' and the language was based on an old model of [[UCSD Pascal]], which makes it possible to generate interpretive code. |title=History of Java|work=Java Application Servers Report|author=TechMetrix Research|year=1999|archive-url=https://web.archive.org/web/20101229090912/http://www.fscript.org/prof/javapassport.pdf|archive-date=December 29, 2010|url-status=dead}}</ref><ref>{{cite magazine |title=A Conversation with James Gosling |magazine=[[ACM Queue]] |date=August 31, 2004 |url=http://queue.acm.org/detail.cfm?id=1017013 |publisher=[[Association for Computing Machinery]] |volume=2 |issue=5 |access-date=2010-06-09|archive-url=https://web.archive.org/web/20150716194245/http://queue.acm.org/detail.cfm?id=1017013|archive-date=July 16, 2015 |url-status=live}}</ref> [[Object Pascal]]<ref>{{cite report |author=((The Java Language Team)) |publisher=JavaSoft, Sun Microsystems, Inc. |url=http://java.sun.com/docs/white/delegates.html |quote=In the summer of 1996, Sun was designing the precursor to what is now the event model of the AWT and the JavaBeans component architecture. Borland contributed greatly to this process. We looked very carefully at Delphi Object Pascal and built a working prototype of bound method references in order to understand their interaction with the Java programming language and its APIs. |archive-url=https://web.archive.org/web/20120627043929/http://java.sun.com/docs/white/delegates.html |archive-date=2012-06-27 |url-status=dead |type=White Paper |title=About Microsoft's 'Delegates'}}</ref> | influenced = [[Ada (programming language)|Ada 2005]], [[ArkTS]], [[BeanShell]], [[C Sharp (programming language)|C#]], [[Chapel (programming language)|Chapel]],<ref name="chplspec">{{cite web|title=Chapel spec (Acknowledgements)|url=http://chapel.cray.com/spec/spec-0.98.pdf|date=2015-10-01|access-date=2016-01-14|publisher=Cray Inc.|archive-url=https://web.archive.org/web/20160205114946/http://chapel.cray.com/spec/spec-0.98.pdf|archive-date=February 5, 2016|url-status=live}}</ref> [[Clojure]], [[ECMAScript]], [[Fantom (programming language)|Fantom]], [[Gambas]],<ref name="gambas">{{cite web|url=http://gambaswiki.org/wiki/doc/intro?nh&l=en|title=Gambas Documentation Introduction|publisher=Gambas Website|access-date=2017-10-09|archive-url=https://web.archive.org/web/20171009041815/http://gambaswiki.org/wiki/doc/intro?nh&l=en|archive-date=October 9, 2017|url-status=live}}</ref> [[Apache Groovy|Groovy]], [[Hack (programming language)|Hack]],<ref>{{cite magazine|url=http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|title=Facebook Q&A: Hack brings static typing to PHP world|magazine=InfoWorld|date=March 26, 2014|access-date=2015-01-11|archive-url=https://web.archive.org/web/20150213220946/http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|archive-date=February 13, 2015|url-status=live}}</ref> [[Haxe]], [[Visual J Sharp|J#]], [[JavaScript]], [[JS++]], [[Kotlin]], [[PHP]], [[Python (programming language)|Python]], [[Scala (programming language)|Scala]], [[Vala (programming language)|Vala]] | website = {{ubl|{{URL|oracle.com/java/}}|{{URL|java.com}}|{{URL|dev.java}}}} | file_ext = .java, [[Java class file|.class]], [[JAR (file format)|.jar]], .jmod, [[WAR (file format)|.war]] | wikibooks = Java Programming }} {{Java sidebar}} '''Java''' is a [[High-level programming language|high-level]], [[General-purpose programming language|general-purpose]], [[Memory safety|memory-safe]], [[object-oriented programming|object-oriented]] [[programming language]]. It is intended to let [[programmer]]s ''write once, run anywhere'' ([[Write once, run anywhere|WORA]]),<ref>{{cite web|title=Write once, run anywhere?|date=May 2, 2002 |publisher=[[Computer Weekly]] |url=http://www.computerweekly.com/Articles/2002/05/02/186793/write-once-run-anywhere.htm|access-date=2009-07-27|url-status=live|archive-date=August 13, 2021|archive-url=https://web.archive.org/web/20210813193857/https://www.computerweekly.com/feature/Write-once-run-anywhere}}</ref> meaning that [[compiler|compiled]] Java code can run on all platforms that support Java without the need to recompile.<ref name="design_goals">{{cite web |title=1.2 Design Goals of the Java Programming Language|date=January 1, 1999 |url=https://www.oracle.com/technetwork/java/intro-141325.html|access-date=2013-01-14|publisher=Oracle|archive-url=https://web.archive.org/web/20130123204103/http://www.oracle.com/technetwork/java/intro-141325.html|archive-date=January 23, 2013|url-status=live}}</ref> Java applications are typically compiled to [[Java bytecode|bytecode]] that can run on any [[Java virtual machine]] (JVM) regardless of the underlying [[computer architecture]]. The [[syntax (programming languages)|syntax]] of Java is similar to [[C (programming language)|C]] and [[C++]], but has fewer [[low-level programming language|low-level]] facilities than either of them. The Java runtime provides dynamic capabilities (such as [[Reflective programming|reflection]] and runtime code modification) that are typically not available in traditional compiled languages. Java gained popularity shortly after its release, and has been a popular programming language since then.<ref>{{Cite web |last=Melanson |first=Mike |date=August 9, 2022 |title=Don't call it a comeback: Why Java is still champ |url=https://github.com/readme/featured/java-programming-language |url-status=live |archive-url=https://web.archive.org/web/20230825195416/https://github.com/readme/featured/java-programming-language |archive-date=August 25, 2023 |access-date=October 15, 2023 |website=[[GitHub]]}}</ref> Java was the third most popular programming language in {{As of|2022|bare=yes}} according to [[GitHub]].<ref>{{Cite web |title=The top programming languages |url=https://octoverse.github.com/2022/top-programming-languages |url-status=live |archive-url=https://web.archive.org/web/20230802203718/https://octoverse.github.com/2022/top-programming-languages |archive-date=2 August 2023 |access-date=15 October 2023 |website=The State of the Octoverse |publisher=[[GitHub]]}}</ref> Although still widely popular, there has been a gradual decline in use of Java in recent years with [[List of JVM languages|other languages using JVM]] gaining popularity.<ref name=":0">{{cite magazine |last=McMillan |first=Robert |date=August 1, 2013 |title=Is Java Losing Its Mojo? |url=https://www.wired.com/2013/01/java-no-longer-a-favorite/ |url-access=limited |url-status=live |magazine=[[wired.com|Wired]] |archive-url=https://web.archive.org/web/20170215115409/https://www.wired.com/2013/01/java-no-longer-a-favorite/ |archive-date=February 15, 2017 |access-date=October 15, 2023 |quote=}}</ref> Java was designed by [[James Gosling]] at [[Sun Microsystems]]. It was released in May 1995 as a core component of Sun's [[Java (software platform)|Java platform]]. The original and [[reference implementation]] Java [[compiler]]s, virtual machines, and [[library (computing)|class libraries]] were released by Sun under [[proprietary license]]s. As of May 2007, in compliance with the specifications of the [[Java Community Process]], Sun had [[Software relicensing|relicensed]] most of its Java technologies under the [[GNU General Public License|GPL-2.0-only]] license. [[Oracle Corporation|Oracle]], which bought Sun in 2010, offers its own [[HotSpot]] Java virtual machine. However, the official [[reference implementation]] is the [[OpenJDK]] JVM, which is open-source software used by most developers and is the default JVM for almost all [[Linux distribution]]s. [[Java version history|Java 26]] is the current version {{as of|lc=y|2026|March}}. Java 25 is [[long-term support]] (LTS) version still under maintenance by Oracle (as [[permissive license|permissively licensed]]); Java 21 is also still an LTS version though users "wanting to continue with permissively licensed versions of Java after September of 2026 should upgrade to Oracle JDK 25 or later"<ref>{{Cite web |title=Oracle Java SE Support Roadmap |url=https://www.oracle.com/java/technologies/java-se-support-roadmap.html |access-date=2026-04-12 |website=www.oracle.com |language=en-US}}</ref> according to Oracle. Oracle also provides proprietary "Java SE OTN license" for it (for longer) and Java 21 LTS, 11 LTS and 8 LTS. Note, Oracle still supports Java 8 LTS at no cost (but with a [[proprietary license]]) for ''personal'' use. Others also support same LTS versions (commercially), and latest, and some even down to Java 6 and 7 (to 2027 or March 2028 depending). ==ايڊيشن== ==عملدرآمد سسٽم== ==نحو== ==خاص ڪلاس== ==تنقيد== ==ڪلاس لائبريريون== ==دستاويزون== ==عملدرآمد== ==جاوا پليٽ فارم کان ٻاهر استعمال== جاوا پروگرامنگ ٻولي کي سافٽ ويئر پليٽ فارم جي موجودگي جي ضرورت آهي ترتيب ڏنل پروگرامن تي عمل ڪرڻ لاء. اوريڪل (Oracle) جاوا سان استعمال ڪرڻ لاءِ جاوا پليٽ فارم فراهم ڪري ٿو. اینڊروئڊ ایس ڊي ڪي (Android SDK) هڪ متبادل سافٽ ويئر پليٽ فارم آهي، جيڪو بنيادي طور تي پنهنجي جي یو آء (GUI) سسٽم سان اینڊروئڊ ايپليڪيشنون ٺاهڻ لاءِ استعمال ڪيو ويندو آهي. ===اینڊروئڊ=== جاوا ٻولي اینڊروئڊ، هڪ کليل ذريعو موبائل آپريٽنگ سسٽم، ۾ هڪ اهم ستون آهي. جيتوڻيڪ اینڊروئڊ، لینوڪس ڪرنیل (Linux kernel) تي ٺهيل آهي، گهڻو ڪري "C" بولی ۾ لکيو ويو آهي، اینڊروئڊ ایس ڊي ڪي، اینڊروئڊ ايپليڪيشنن لاءِ بنياد طور جاوا ٻولي استعمال ڪري ٿو پر ان جي معياري جي.یو.آء (GUI)، ایس.اي. (SE)، ایم.اي. (ME) يا ٻيون قائم ڪيل جاوا معيار استعمال نٿو ڪري. اینڊروئڊ ایس.ڊي.ڪي. پاران سپورٽ ڪيل بائٽ ڪوڊ ٻولي (bytecode language) جاوا بائٽ ڪوڊ سان مطابقت نه رکي ٿي ۽ پنھنجي ورچوئل مشين تي ھلندي آھي، گھٽ ميموري ڊيوائسز جھڙوڪ اسمارٽ فونز ۽ ٽيبليٽ ڪمپيوٽرن لاءِ بھتر آھي. اینڊروئڊ ورزن تي مدار رکندي، بائيٽ ڪوڊ يا ته ڊالڪ ورچوئل مشين جي ذريعي تفسير ڪيو ويو آهي يا اینڊروئڊ رن ٽائم پاران اصلي ڪوڊ ۾ مرتب ڪيو ويو آهي. اینڊروئڊ مڪمل جاوا ایس.اي. معياري لائبريري مهيا نٿو ڪري، جيتوڻيڪ اینڊروئڊ ایس.ڊي.ڪي. ۾ ان جي وڏي سب سیٽ جو هڪ آزاد عمل شامل آهي. اهو جاوا 6 ۽ ڪجهه جاوا 7 خاصيتن کي سپورٽ ڪري ٿو، معياري لائبريري (Apache Harmony) سان مطابقت رکندڙ عمل درآمد پيش ڪري ٿو. ===تڪرار=== گوگل انڪارپوریشن، اینڊروئڊ ۾ جاوا سان لاڳاپيل ٽيڪنالاجي جو استعمال اوريڪل انڪارپوریشن ۽ گوگل انڪارپوریشن جي وچ ۾ قانوني تڪرار جو سبب بڻيو. 7 مئي 2012ع تي، هڪ سان فرانسسڪو جيوري معلوم ڪيو ته جيڪڏهن اي.پي.آء (APIs) ڪاپي رائيٽ ٿي سگهي ٿي، ته پوءِ گوگل اینڊروئڊ ڊیوائيسز ۾ جاوا جي استعمال سان اوريڪل جي ڪاپي رائيٽ جي خلاف ورزي ڪئي هئي. ضلعي جج وليم السپ 31 مئي، 2012ع تي فيصلو ڏنو ته اي.پي.آء ڪاپي رائيٽ نٿا ٿي سگهن، پر مئي، 2014ع ۾ آمريڪي عدالت آف اپيلز فار فيڊرل سرڪٽ طرفان ان کي رد ڪيو ويو. 26 مئي، 2016ع تي، ضلعي عدالت گوگل جي حق ۾ فيصلو ڏنو. اینڊروئڊ ۾ جاوا اي.پي.آء جي ڪاپي رائيٽ جي خلاف ورزي جي حڪمراني منصفانه استعمال کي قائم ڪري ٿي. مارچ 2018ع ۾، هي حڪمران اپيل ڪورٽ طرفان رد ڪيو ويو، جنهن سان فرانسسڪو ۾ وفاقي عدالت کي نقصان جي تعين ڪرڻ جو ڪيس موڪليو ويو. گوگل جنوري 2019ع ۾ آمريڪا جي سپريم ڪورٽ ۾ سرٽيوريري جي رٽ لاءِ هڪ درخواست داخل ڪئي ته انهن ٻن حڪمن کي چيلينج ڪرڻ لاءِ جيڪي اپيل ڪورٽ طرفان اوريڪل جي حق ۾ ڪيا ويا. 5 اپريل، 2021ع تي، عدالت گوگل جي حق ۾ 6-2 جو فيصلو ڪيو، ته جاوا اي.پي.آء جي استعمال کي مناسب استعمال سمجهيو وڃي. تنهن هوندي، عدالت اي.پي.آء جي ڪاپي رائيٽ تي حڪمراني ڪرڻ کان انڪار ڪري ڇڏيو، ان جي بدران چونڊ ڪري انهن جي حڪمراني جو تعين ڪرڻ لاءِ، "خالص دليل جي خاطر" جاوا جي اي.پي.آء. ڪاپي رائيٽ قابل غور ڪندي. ==پڻ ڏسو== {{Portal|ڪمپيوٽر پروگرامنگ}} * سي شارپ (#C) پروگرامنگ جي ٻولي * سي ++ (++C) * جاوا APIs جي فهرست * جاوا فريم ورڪ جي فهرست * JVM ٻولين جي فهرست * جاوا ورچوئل مشينن جي فهرست * سي شارپ ۽ جاوا جو موازنو * جاوا ۽ C++ جو موازنو * پروگرامنگ ٻولين جو موازنو ==حوالا== {{حوالا}} ==خارجي لنڪس== * * {{Commons-inline}} * {{Wikibooks-inline|Java Programming}} * [https://discu.eu/weekly/java/ ''Java Weekly''] {{Webarchive|url=https://web.archive.org/web/20240822213928/https://discu.eu/weekly/java/ |date=2024-08-22 }} {{Authority control}} [[زمرو:جاوا (پروگرامنگ ٻولي)|جاوا]] [[زمرو:پروگرامنگ ٻوليون]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر ٻوليون]] [[زمرو:سن مائڪرو سسٽم]] [[زمرو:JVM پروگرامنگ ٻوليون]] [[زمرو:سي پروگرامنگ ٻولي خاندان]] [[زمرو:سي پروگرامنگ ٻولي]] [[زمرو:مرتب ڪيل پروگرامنگ ٻوليون]] [[زمرو:ڪلاس تي ٻڌل پروگرامنگ ٻوليون]] [[زمرو:هم آهنگ پروگرامنگ ٻوليون]] [[زمرو:ملٽي پيراڊائم پروگرامنگ ٻوليون]] [[زمرو:جاوا پليٽ فارم|پروگرامنگ ٻولي]] [[زمرو:1995 ۾ ٺاهيل پروگرامنگ ٻوليون]] [[زمرو:مضمون مثال طور جاوا ڪوڊ]] [[زمرو:جاوا وضاحت جي درخواستون|پروگرامنگ ٻولي]] [[زمرو:جامد ٽائيپ ٿيل پروگرامنگ ٻوليون]] [[زمرو:اعتراض تي مبني پروگرامنگ ٻوليون]] mb705r3sbnwjgsjoj03e75faldtar6x 371874 371873 2026-04-17T11:37:43Z Ibne maryam 17680 371874 wikitext text/x-wiki {{Short description|Object-oriented programming language}} {{Distinguish|Java (software platform)|JavaScript|Java |Javanese language}} {{Infobox language | name = Java | logo = Java programming language logo.svg | logo size = 121px | logo caption = | paradigm = [[Programming paradigm#Multi-paradigm|Multi-paradigm]]: [[generic programming|generic]], [[object-oriented]] ([[class-based programming|class-based]]), [[functional programming|functional]], [[imperative programming|imperative]], [[reflection (computer programming)|reflective]], [[concurrent computing|concurrent]] | year = {{Start date and age|1995|5|23}}<ref>{{cite magazine|url=https://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|title=Java's 20 Years of Innovation|magazine=Forbes|date=May 20, 2015|access-date=March 18, 2016|author=Binstock, Andrew|archive-url=https://web.archive.org/web/20160314102242/http://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|archive-date=March 14, 2016|url-status=live}}</ref> | discontinued = <!-- Set to yes if software is discontinued, otherwise omit. --> | ver layout = <!-- simple (default) or stacked --> | latest release version = {{wikidata|property|edit|reference|P548=Q2804309|P348}} | latest release date = {{start date and age|{{wikidata|qualifier|single|P548=Q2804309|P348|P577}}}} | designer = [[James Gosling]] | developer = [[Oracle Corporation]] | typing = [[type system|Static, strong, safe]], [[nominal type system|nominative]], [[manifest typing|manifest]] | memory management = [[Garbage collection (computer science)|Automatic garbage collection]] | influenced_by = [[CLU (programming language)|CLU]],<ref name="BarbaraLiskov">{{cite book |title=Program Development in Java - Abstraction, Specification, and Object-Oriented Design|author=[[Barbara Liskov]] with [[John Guttag]]|isbn=9780201657685|publisher=USA, Addison Wesley|year=2000}}</ref> [[Simula67]],<ref name="BarbaraLiskov"/> [[Lisp (programming language)|Lisp]],<ref name="BarbaraLiskov"/> [[Smalltalk]],<ref name="BarbaraLiskov"/> [[Ada (programming language)|Ada 83]], [[C++]],<ref>{{cite web|url=https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133|title=Cracking The Java Programming Interview :: 2000+ Java Interview Que/Ans|first=Harry H.|last=Chaudhary|access-date=2016-05-29|date=2014-07-28|archive-date=September 29, 2023|archive-url=https://web.archive.org/web/20230929040943/https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133#v=onepage&q&f=false|url-status=live}}</ref> [[C Sharp (programming language)|C#]],<ref>Java&nbsp;5.0 added several new language features (the [[foreach loop|enhanced for loop]], [[object type (object-oriented programming)#Autoboxing|autoboxing]], [[variadic function|varargs]] and [[Java annotation|annotations]]), after they were introduced in the similar (and competing) [[C Sharp (programming language)|C#]] language. [http://www.barrycornelius.com/papers/java5/] {{Webarchive|url=https://web.archive.org/web/20110319065438/http://www.barrycornelius.com/papers/java5/|date=March 19, 2011}} [http://www.levenez.com/lang/] {{Webarchive|url=https://web.archive.org/web/20060107162045/http://www.levenez.com/lang/|date=January 7, 2006}}</ref> [[Eiffel (programming language)|Eiffel]],<ref>{{cite web|author1=Gosling, James|author2=McGilton, Henry|title=The Java Language Environment|date=May 1996|url=https://www.oracle.com/technetwork/java/langenv-140151.html|access-date=May 6, 2014|archive-url=https://web.archive.org/web/20140506214653/http://www.oracle.com/technetwork/java/langenv-140151.html|archive-date=May 6, 2014 |url-status=live}}</ref> [[Mesa (programming language)|Mesa]],<ref>{{cite web|author1=Gosling, James|author2=Joy, Bill |author3=Steele, Guy|author4=Bracha, Gilad|title=The Java Language Specification, 2nd Edition |url=https://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|access-date=February 8, 2008|archive-url=https://web.archive.org/web/20110805051057/http://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|archive-date=August 5, 2011 |url-status=live}}</ref> [[Modula-3]],<ref>{{cite web |url=http://www.computerworld.com.au/index.php/id;1422447371;pp;3;fp;4194304;fpid;1|title=The A-Z of Programming Languages: Modula-3 |publisher=Computerworld|access-date=2010-06-09|url-status=dead|archive-url=https://web.archive.org/web/20090105145818/http://www.computerworld.com.au/index.php/id%3B1422447371%3Bpp%3B3%3Bfp%3B4194304%3Bfpid%3B1|archive-date=January 5, 2009}}</ref> [[Oberon (programming language)|Oberon]],<ref>[[Niklaus Wirth]] stated on a number of public occasions, e.g. in a lecture at the Polytechnic Museum, Moscow in September 2005 (several independent first-hand accounts in Russian exist, e.g. one with an audio recording: {{cite web|author=Filippova, Elena|title=Niklaus Wirth's lecture at the Polytechnic Museum in Moscow|date=September 22, 2005|url=http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|access-date=November 20, 2011|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201054813/http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|url-status=live}}), that the Sun Java design team licensed the Oberon compiler sources a number of years prior to the release of Java and examined it: a (relative) compactness, type safety, garbage collection, no multiple inheritance for classes{{snd}} all these key overall design features are shared by Java and Oberon.</ref> [[Objective-C]],<ref>[[Patrick Naughton]] cites [[Objective-C]] as a strong influence on the design of the Java programming language, stating that notable direct derivatives include Java interfaces (derived from Objective-C's [[Objective-C#Protocols|protocol]]) and primitive wrapper classes. [http://cs.gmu.edu/~sean/stuff/java-objc.html] {{Webarchive|url=https://web.archive.org/web/20110713014816/http://cs.gmu.edu/~sean/stuff/java-objc.html|date=July 13, 2011}}</ref> [[UCSD Pascal]],<ref>{{cite web |url=http://www.fscript.org/prof/javapassport.pdf |quote=The project went ahead under the name ''green'' and the language was based on an old model of [[UCSD Pascal]], which makes it possible to generate interpretive code. |title=History of Java|work=Java Application Servers Report|author=TechMetrix Research|year=1999|archive-url=https://web.archive.org/web/20101229090912/http://www.fscript.org/prof/javapassport.pdf|archive-date=December 29, 2010|url-status=dead}}</ref><ref>{{cite web |title=A Conversation with James Gosling – ACM Queue |date=August 31, 2004 |url=http://queue.acm.org/detail.cfm?id=1017013 |publisher=Queue.acm.org |access-date=2010-06-09|archive-url=https://web.archive.org/web/20150716194245/http://queue.acm.org/detail.cfm?id=1017013|archive-date=July 16, 2015 |url-status=live}}</ref> [[Object Pascal]]<ref>{{cite report |author=((The Java Language Team)) |publisher=JavaSoft, Sun Microsystems, Inc. |url=http://java.sun.com/docs/white/delegates.html |quote=In the summer of 1996, Sun was designing the precursor to what is now the event model of the AWT and the JavaBeans component architecture. Borland contributed greatly to this process. We looked very carefully at Delphi Object Pascal and built a working prototype of bound method references in order to understand their interaction with the Java programming language and its APIs. |archive-url=https://web.archive.org/web/20120627043929/http://java.sun.com/docs/white/delegates.html |archive-date=2012-06-27 |url-status=dead |type=White Paper |title=About Microsoft's "Delegates"}}</ref> | influenced = [[Ada (programming language)|Ada 2005]], [[BeanShell]], [[C Sharp (programming language)|C#]], [[Chapel (programming language)|Chapel]],<ref name="chplspec">{{cite web|title=Chapel spec (Acknowledgements)|url=http://chapel.cray.com/spec/spec-0.98.pdf|date=2015-10-01|access-date=2016-01-14|publisher=Cray Inc.|archive-url=https://web.archive.org/web/20160205114946/http://chapel.cray.com/spec/spec-0.98.pdf|archive-date=February 5, 2016|url-status=live}}</ref> [[Clojure]], [[ECMAScript]], [[Fantom (programming language)|Fantom]], [[Gambas]],<ref name="gambas">{{cite web|url=http://gambaswiki.org/wiki/doc/intro?nh&l=en|title=Gambas Documentation Introduction|publisher=Gambas Website|access-date=2017-10-09|archive-url=https://web.archive.org/web/20171009041815/http://gambaswiki.org/wiki/doc/intro?nh&l=en|archive-date=October 9, 2017|url-status=live}}</ref> [[Groovy (programming language)|Groovy]], [[Hack (programming language)|Hack]],<ref>{{cite magazine|url=http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|title=Facebook Q&A: Hack brings static typing to PHP world|magazine=InfoWorld|date=March 26, 2014|access-date=2015-01-11|archive-url=https://web.archive.org/web/20150213220946/http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|archive-date=February 13, 2015|url-status=live}}</ref> [[Haxe]], [[Visual J Sharp|J#]], [[Kotlin (programming language)|Kotlin]], [[PHP]], [[Python (programming language)|Python]], [[Scala (programming language)|Scala]], [[Seed7]], [[Vala (programming language)|Vala]], [[JavaScript]], [[JS++]], [[ArkTS]] | website = {{ubl|{{URL|oracle.com/java/}}|{{URL|java.com}}|{{URL|dev.java}}}} | file_ext = .java, [[Java class file|.class]], [[JAR (file format)|.jar]], .jmod | wikibooks = Java Programming }} [[File:Duke (Java mascot) waving.svg|thumb|upright=0.5|Duke, the Java mascot]] [[File:James Gosling 2008.jpg|thumb|[[James Gosling]], the creator of Java, in 2008]] '''جاوا''' (Java) هڪ اعليٰ سطحي، ڪلاس تي ٻڌل، مقصد تي مبني پروگرامنگ ٻولي آهي. اها هڪ عام مقصدي پروگرامنگ ٻولي آهي جنهن جو مقصد پروگرامرن کي هڪ ڀيرو لکڻ، ڪٿي به هلائڻ (WORA) جی سھولت ڏيڻ آهي،<ref>{{cite web|url=http://www.computerweekly.com/Articles/2002/05/02/186793/write-once-run-anywhere.htm|title=Write once, run anywhere?|date=May 2, 2002|publisher=[[Computer Weekly]]|archive-url=https://web.archive.org/web/20210813193857/https://www.computerweekly.com/feature/Write-once-run-anywhere|archive-date=August 13, 2021|access-date=2009-07-27|url-status=live}}</ref> مطلب ته مرتب ڪيل جاوا ڪوڊ انهن سڀني پليٽ فارمن تي، بغير ڪنهن کي ٻيهر ٺاهڻ جي، هلائي سگهي ٿو جيڪي جاوا کي سپورٽ ڪن ٿيون. <ref name="design_goals2">{{cite web|url=https://www.oracle.com/technetwork/java/intro-141325.html|title=1.2 Design Goals of the Java Programming Language|date=January 1, 1999|publisher=Oracle|archive-url=https://web.archive.org/web/20130123204103/http://www.oracle.com/technetwork/java/intro-141325.html|archive-date=January 23, 2013|access-date=2013-01-14|url-status=live}}</ref>جاوا ايپليڪيشنون عام طور تي بائيٽ ڪوڊ تي مرتب ٿيل آهن جيڪي ڪنهن به جاوا ورچوئل مشين (JVM) تي هلائي سگهن ٿيون بغير ڪنهن بنيادي ڪمپيوٽر جي فن تعمير جي. جاوا جو نحو C ۽ C++ سان ملندڙ جلندڙ آهي، پر انهن مان ڪنهن به هڪ جي ڀيٽ ۾ گهٽ گهٽ-سطح جون سهولتون آهن. جاوا رن ٽائم متحرڪ صلاحيتون مهيا ڪري ٿو (جهڙوڪ عڪاسي ۽ رن ٽائم ڪوڊ ترميم) جيڪي عام طور تي روايتي مرتب ڪيل ٻولين ۾ موجود نه آهن. جاوا پنهنجي ریليز ٿيڻ کان پوءِ جلدي مقبوليت حاصل ڪئي ۽ ان وقت کان وٺي هڪ تمام مشهور پروگرامنگ ٻولي رهي آهي.<ref>{{Cite web|url=https://github.com/readme/featured/java-programming-language|title=Don't call it a comeback: Why Java is still champ|last=Melanson|first=Mike|date=August 9, 2022|website=[[GitHub]]|archive-url=https://web.archive.org/web/20230825195416/https://github.com/readme/featured/java-programming-language|archive-date=August 25, 2023|access-date=October 15, 2023|url-status=live}}</ref> GitHub جي مطابق سال 2022ع ۾ جاوا ٽيون مقبول ترين پروگرامنگ ٻولي هئي.<ref>{{Cite web|url=https://octoverse.github.com/2022/top-programming-languages|title=The top programming languages|website=The State of the Octoverse|publisher=[[GitHub]]|archive-url=https://web.archive.org/web/20230802203718/https://octoverse.github.com/2022/top-programming-languages|archive-date=2 August 2023|access-date=15 October 2023|url-status=live}}</ref> جيتوڻيڪ اڃا تائين وڏي پيماني تي مشهور آهي، تازو سالن ۾ جاوا جي استعمال ۾ بتدريج گهٽتائي آئي آهي ٻين ٻولين سان گڏ JVM استعمال ڪندي مقبوليت حاصل ڪئي.<ref name=":02">{{cite magazine|last=McMillan|first=Robert|date=August 1, 2013|title=Is Java Losing Its Mojo?|url=https://www.wired.com/2013/01/java-no-longer-a-favorite/|url-access=limited|url-status=live|magazine=[[wired.com|Wired]]|archive-url=https://web.archive.org/web/20170215115409/https://www.wired.com/2013/01/java-no-longer-a-favorite/|archive-date=February 15, 2017|access-date=October 15, 2023|quote=}}</ref> جاوا اصل ۾ جيمز گوسلنگ پاران سن مائڪرو سسٽم ۾ ترقي ڪئي وئي هئي. اهو مئي 1995ع ۾ سن جي جاوا پليٽ فارم جي بنيادي جزو طور جاري ڪيو ويو. اصل ۽ حوالن تي عملدرآمد جاوا ڪمپليرز، ورچوئل مشينون، ۽ ڪلاس لائبرريون اصل ۾ سن پاران مالڪاڻي لائسنس تحت جاري ڪيون ويون. مئي 2007ع تائين، جاوا ڪميونٽي پروسيس جي وضاحتن جي تعميل ۾، سن پنهنجي اڪثر جاوا ٽيڪنالاجيز کي GPL-2.0-صرف لائسنس تحت لائسنس ڏنو هو. Oracle پيش ڪري ٿو پنهنجي HotSpot جاوا ورچوئل مشين، جڏهن ته سرڪاري حوالن تي عمل درآمد OpenJDK JVM آهي جيڪو مفت اوپن سورس سافٽ ويئر آهي ۽ اڪثر ڊولپرز پاران استعمال ڪيو ويندو آهي ۽ تقريبن سڀني لينڪس جي تقسيم لاءِ ڊفالٽ JVM آهي. 2024ع تائين، جاوا 22 جديد نسخو آهي. جاوا 8، 11، 17، ۽ 21 اڳوڻو LTS ورزن آھن اڃا تائين سرڪاري طور تي سپورٽ ٿيل آھن. ==تاريخ== {{Short description|Object-oriented programming language}} {{Distinguish|JavaScript}} {{Infobox settlement | name = Java | logo = Java programming language logo.svg | logo size = 121px | logo caption = | paradigm = [[Programming paradigm#Multi-paradigm|Multi-paradigm]]: [[generic programming|generic]], [[Object-oriented programming|object-oriented]] ([[class-based programming|class-based]]), [[functional programming|functional]], [[imperative programming|imperative]], [[reflective programming|reflective]], [[concurrent computing|concurrent]] | year = {{Start date and age|1995|5|23}}<ref>{{cite magazine|url=https://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|title=Java's 20 Years of Innovation|magazine=Forbes|date=May 20, 2015|access-date=March 18, 2016|author=Binstock, Andrew|archive-url=https://web.archive.org/web/20160314102242/http://www.forbes.com/sites/oracle/2015/05/20/javas-20-years-of-innovation/|archive-date=March 14, 2016|url-status=live}}</ref> | latest release version = {{wikidata|property|preferred|references|edit|Q251|P348}} | latest release date = {{Start date and age|{{wikidata|qualifier|preferred|single|Q251|P348|P577}}}} | designer = [[James Gosling]] | developer = [[Oracle Corporation]] | typing = [[type system|Static, strong, safe]], [[nominal type system|nominative]], [[manifest typing|manifest]] | memory management = [[Garbage collection (computer science)|Garbage-collected]] | influenced_by = [[CLU (programming language)|CLU]],<ref name="BarbaraLiskov">{{cite book |title=Program Development in Java – Abstraction, Specification, and Object-Oriented Design|author=[[Barbara Liskov]] with [[John Guttag]]|isbn=978-0-201-65768-5|publisher=USA, Addison Wesley|year=2000}}</ref> [[Simula67]],<ref name="BarbaraLiskov" /> [[Lisp (programming language)|Lisp]],<ref name="BarbaraLiskov" /> [[Smalltalk]],<ref name="BarbaraLiskov" /> [[Ada (programming language)|Ada 83]], [[C++]],<ref>{{cite web|url=https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133|title=Cracking The Java Programming Interview :: 2000+ Java Interview Que/Ans|first=Harry H.|last=Chaudhary|access-date=2016-05-29|date=2014-07-28|archive-date=September 29, 2023|archive-url=https://web.archive.org/web/20230929040943/https://books.google.com/books?id=0rUtBAAAQBAJ&pg=PAPA133#v=onepage&q&f=false|url-status=live}}</ref> [[C Sharp (programming language)|C#]],<ref>Java&nbsp;5.0 added several new language features (the [[foreach loop|enhanced for loop]], [[object type (object-oriented programming)#Autoboxing|autoboxing]], [[variadic function|varargs]] and [[Java annotation|annotations]]), after they were introduced in the similar (and competing) [[C Sharp (programming language)|C#]] language. [http://www.barrycornelius.com/papers/java5/] {{Webarchive|url=https://web.archive.org/web/20110319065438/http://www.barrycornelius.com/papers/java5/|date=March 19, 2011}} [http://www.levenez.com/lang/] {{Webarchive|url=https://web.archive.org/web/20060107162045/http://www.levenez.com/lang/|date=January 7, 2006}}</ref> [[Eiffel (programming language)|Eiffel]],<ref>{{cite web|author1=Gosling, James|author2=McGilton, Henry|title=The Java Language Environment|date=May 1996|url=https://www.oracle.com/technetwork/java/langenv-140151.html|access-date=May 6, 2014|archive-url=https://web.archive.org/web/20140506214653/http://www.oracle.com/technetwork/java/langenv-140151.html|archive-date=May 6, 2014 |url-status=live}}</ref> [[Mesa (programming language)|Mesa]],<ref>{{cite web|author1=Gosling, James|author2=Joy, Bill |author3=Steele, Guy|author4=Bracha, Gilad|title=The Java Language Specification, 2nd Edition |url=https://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|access-date=February 8, 2008|archive-url=https://web.archive.org/web/20110805051057/http://java.sun.com/docs/books/jls/second_edition/html/intro.doc.html#237601|archive-date=August 5, 2011 |url-status=live}}</ref> [[Modula-3]],<ref>{{cite web |url=http://www.computerworld.com.au/index.php/id;1422447371;pp;3;fp;4194304;fpid;1|title=The A-Z of Programming Languages: Modula-3 |publisher=Computerworld|access-date=2010-06-09|url-status=dead|archive-url=https://web.archive.org/web/20090105145818/http://www.computerworld.com.au/index.php/id%3B1422447371%3Bpp%3B3%3Bfp%3B4194304%3Bfpid%3B1|archive-date=January 5, 2009}}</ref> [[Oberon (programming language)|Oberon]],<ref>[[Niklaus Wirth]] stated on a number of public occasions, e.g. in a lecture at the Polytechnic Museum, Moscow in September 2005 (several independent first-hand accounts in Russian exist, e.g. one with an audio recording: {{cite web|author=Filippova, Elena|title=Niklaus Wirth's lecture at the Polytechnic Museum in Moscow|date=September 22, 2005|url=http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|access-date=November 20, 2011|archive-date=December 1, 2020|archive-url=https://web.archive.org/web/20201201054813/http://www.delphikingdom.com/asp/viewitem.asp?catalogid=1155|url-status=live}}), that the Sun Java design team licensed the Oberon compiler sources a number of years prior to the release of Java and examined it: a (relative) compactness, type safety, garbage collection, no multiple inheritance for classes{{snd}} all these key overall design features are shared by Java and Oberon.</ref> [[Objective-C]],<ref>[[Patrick Naughton]] cites [[Objective-C]] as a strong influence on the design of the Java programming language, stating that notable direct derivatives include Java interfaces (derived from Objective-C's [[Objective-C#Protocols|protocol]]) and primitive wrapper classes. [http://cs.gmu.edu/~sean/stuff/java-objc.html] {{Webarchive|url=https://web.archive.org/web/20110713014816/http://cs.gmu.edu/~sean/stuff/java-objc.html|date=July 13, 2011}}</ref> [[UCSD Pascal]],<ref>{{cite web |url=http://www.fscript.org/prof/javapassport.pdf |quote=The project went ahead under the name ''green'' and the language was based on an old model of [[UCSD Pascal]], which makes it possible to generate interpretive code. |title=History of Java|work=Java Application Servers Report|author=TechMetrix Research|year=1999|archive-url=https://web.archive.org/web/20101229090912/http://www.fscript.org/prof/javapassport.pdf|archive-date=December 29, 2010|url-status=dead}}</ref><ref>{{cite magazine |title=A Conversation with James Gosling |magazine=[[ACM Queue]] |date=August 31, 2004 |url=http://queue.acm.org/detail.cfm?id=1017013 |publisher=[[Association for Computing Machinery]] |volume=2 |issue=5 |access-date=2010-06-09|archive-url=https://web.archive.org/web/20150716194245/http://queue.acm.org/detail.cfm?id=1017013|archive-date=July 16, 2015 |url-status=live}}</ref> [[Object Pascal]]<ref>{{cite report |author=((The Java Language Team)) |publisher=JavaSoft, Sun Microsystems, Inc. |url=http://java.sun.com/docs/white/delegates.html |quote=In the summer of 1996, Sun was designing the precursor to what is now the event model of the AWT and the JavaBeans component architecture. Borland contributed greatly to this process. We looked very carefully at Delphi Object Pascal and built a working prototype of bound method references in order to understand their interaction with the Java programming language and its APIs. |archive-url=https://web.archive.org/web/20120627043929/http://java.sun.com/docs/white/delegates.html |archive-date=2012-06-27 |url-status=dead |type=White Paper |title=About Microsoft's 'Delegates'}}</ref> | influenced = [[Ada (programming language)|Ada 2005]], [[ArkTS]], [[BeanShell]], [[C Sharp (programming language)|C#]], [[Chapel (programming language)|Chapel]],<ref name="chplspec">{{cite web|title=Chapel spec (Acknowledgements)|url=http://chapel.cray.com/spec/spec-0.98.pdf|date=2015-10-01|access-date=2016-01-14|publisher=Cray Inc.|archive-url=https://web.archive.org/web/20160205114946/http://chapel.cray.com/spec/spec-0.98.pdf|archive-date=February 5, 2016|url-status=live}}</ref> [[Clojure]], [[ECMAScript]], [[Fantom (programming language)|Fantom]], [[Gambas]],<ref name="gambas">{{cite web|url=http://gambaswiki.org/wiki/doc/intro?nh&l=en|title=Gambas Documentation Introduction|publisher=Gambas Website|access-date=2017-10-09|archive-url=https://web.archive.org/web/20171009041815/http://gambaswiki.org/wiki/doc/intro?nh&l=en|archive-date=October 9, 2017|url-status=live}}</ref> [[Apache Groovy|Groovy]], [[Hack (programming language)|Hack]],<ref>{{cite magazine|url=http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|title=Facebook Q&A: Hack brings static typing to PHP world|magazine=InfoWorld|date=March 26, 2014|access-date=2015-01-11|archive-url=https://web.archive.org/web/20150213220946/http://www.infoworld.com/article/2610885/facebook-q-a--hack-brings-static-typing-to-php-world.html|archive-date=February 13, 2015|url-status=live}}</ref> [[Haxe]], [[Visual J Sharp|J#]], [[JavaScript]], [[JS++]], [[Kotlin]], [[PHP]], [[Python (programming language)|Python]], [[Scala (programming language)|Scala]], [[Vala (programming language)|Vala]] | website = {{ubl|{{URL|oracle.com/java/}}|{{URL|java.com}}|{{URL|dev.java}}}} | file_ext = .java, [[Java class file|.class]], [[JAR (file format)|.jar]], .jmod, [[WAR (file format)|.war]] | wikibooks = Java Programming }} {{Java sidebar}} '''Java''' is a [[High-level programming language|high-level]], [[General-purpose programming language|general-purpose]], [[Memory safety|memory-safe]], [[object-oriented programming|object-oriented]] [[programming language]]. It is intended to let [[programmer]]s ''write once, run anywhere'' ([[Write once, run anywhere|WORA]]),<ref>{{cite web|title=Write once, run anywhere?|date=May 2, 2002 |publisher=[[Computer Weekly]] |url=http://www.computerweekly.com/Articles/2002/05/02/186793/write-once-run-anywhere.htm|access-date=2009-07-27|url-status=live|archive-date=August 13, 2021|archive-url=https://web.archive.org/web/20210813193857/https://www.computerweekly.com/feature/Write-once-run-anywhere}}</ref> meaning that [[compiler|compiled]] Java code can run on all platforms that support Java without the need to recompile.<ref name="design_goals">{{cite web |title=1.2 Design Goals of the Java Programming Language|date=January 1, 1999 |url=https://www.oracle.com/technetwork/java/intro-141325.html|access-date=2013-01-14|publisher=Oracle|archive-url=https://web.archive.org/web/20130123204103/http://www.oracle.com/technetwork/java/intro-141325.html|archive-date=January 23, 2013|url-status=live}}</ref> Java applications are typically compiled to [[Java bytecode|bytecode]] that can run on any [[Java virtual machine]] (JVM) regardless of the underlying [[computer architecture]]. The [[syntax (programming languages)|syntax]] of Java is similar to [[C (programming language)|C]] and [[C++]], but has fewer [[low-level programming language|low-level]] facilities than either of them. The Java runtime provides dynamic capabilities (such as [[Reflective programming|reflection]] and runtime code modification) that are typically not available in traditional compiled languages. Java gained popularity shortly after its release, and has been a popular programming language since then.<ref>{{Cite web |last=Melanson |first=Mike |date=August 9, 2022 |title=Don't call it a comeback: Why Java is still champ |url=https://github.com/readme/featured/java-programming-language |url-status=live |archive-url=https://web.archive.org/web/20230825195416/https://github.com/readme/featured/java-programming-language |archive-date=August 25, 2023 |access-date=October 15, 2023 |website=[[GitHub]]}}</ref> Java was the third most popular programming language in {{As of|2022|bare=yes}} according to [[GitHub]].<ref>{{Cite web |title=The top programming languages |url=https://octoverse.github.com/2022/top-programming-languages |url-status=live |archive-url=https://web.archive.org/web/20230802203718/https://octoverse.github.com/2022/top-programming-languages |archive-date=2 August 2023 |access-date=15 October 2023 |website=The State of the Octoverse |publisher=[[GitHub]]}}</ref> Although still widely popular, there has been a gradual decline in use of Java in recent years with [[List of JVM languages|other languages using JVM]] gaining popularity.<ref name=":0">{{cite magazine |last=McMillan |first=Robert |date=August 1, 2013 |title=Is Java Losing Its Mojo? |url=https://www.wired.com/2013/01/java-no-longer-a-favorite/ |url-access=limited |url-status=live |magazine=[[wired.com|Wired]] |archive-url=https://web.archive.org/web/20170215115409/https://www.wired.com/2013/01/java-no-longer-a-favorite/ |archive-date=February 15, 2017 |access-date=October 15, 2023 |quote=}}</ref> Java was designed by [[James Gosling]] at [[Sun Microsystems]]. It was released in May 1995 as a core component of Sun's [[Java (software platform)|Java platform]]. The original and [[reference implementation]] Java [[compiler]]s, virtual machines, and [[library (computing)|class libraries]] were released by Sun under [[proprietary license]]s. As of May 2007, in compliance with the specifications of the [[Java Community Process]], Sun had [[Software relicensing|relicensed]] most of its Java technologies under the [[GNU General Public License|GPL-2.0-only]] license. [[Oracle Corporation|Oracle]], which bought Sun in 2010, offers its own [[HotSpot]] Java virtual machine. However, the official [[reference implementation]] is the [[OpenJDK]] JVM, which is open-source software used by most developers and is the default JVM for almost all [[Linux distribution]]s. [[Java version history|Java 26]] is the current version {{as of|lc=y|2026|March}}. Java 25 is [[long-term support]] (LTS) version still under maintenance by Oracle (as [[permissive license|permissively licensed]]); Java 21 is also still an LTS version though users "wanting to continue with permissively licensed versions of Java after September of 2026 should upgrade to Oracle JDK 25 or later"<ref>{{Cite web |title=Oracle Java SE Support Roadmap |url=https://www.oracle.com/java/technologies/java-se-support-roadmap.html |access-date=2026-04-12 |website=www.oracle.com |language=en-US}}</ref> according to Oracle. Oracle also provides proprietary "Java SE OTN license" for it (for longer) and Java 21 LTS, 11 LTS and 8 LTS. Note, Oracle still supports Java 8 LTS at no cost (but with a [[proprietary license]]) for ''personal'' use. Others also support same LTS versions (commercially), and latest, and some even down to Java 6 and 7 (to 2027 or March 2028 depending). ==ايڊيشن== ==عملدرآمد سسٽم== ==نحو== ==خاص ڪلاس== ==تنقيد== ==ڪلاس لائبريريون== ==دستاويزون== ==عملدرآمد== ==جاوا پليٽ فارم کان ٻاهر استعمال== جاوا پروگرامنگ ٻولي کي سافٽ ويئر پليٽ فارم جي موجودگي جي ضرورت آهي ترتيب ڏنل پروگرامن تي عمل ڪرڻ لاء. اوريڪل (Oracle) جاوا سان استعمال ڪرڻ لاءِ جاوا پليٽ فارم فراهم ڪري ٿو. اینڊروئڊ ایس ڊي ڪي (Android SDK) هڪ متبادل سافٽ ويئر پليٽ فارم آهي، جيڪو بنيادي طور تي پنهنجي جي یو آء (GUI) سسٽم سان اینڊروئڊ ايپليڪيشنون ٺاهڻ لاءِ استعمال ڪيو ويندو آهي. ===اینڊروئڊ=== جاوا ٻولي اینڊروئڊ، هڪ کليل ذريعو موبائل آپريٽنگ سسٽم، ۾ هڪ اهم ستون آهي. جيتوڻيڪ اینڊروئڊ، لینوڪس ڪرنیل (Linux kernel) تي ٺهيل آهي، گهڻو ڪري "C" بولی ۾ لکيو ويو آهي، اینڊروئڊ ایس ڊي ڪي، اینڊروئڊ ايپليڪيشنن لاءِ بنياد طور جاوا ٻولي استعمال ڪري ٿو پر ان جي معياري جي.یو.آء (GUI)، ایس.اي. (SE)، ایم.اي. (ME) يا ٻيون قائم ڪيل جاوا معيار استعمال نٿو ڪري. اینڊروئڊ ایس.ڊي.ڪي. پاران سپورٽ ڪيل بائٽ ڪوڊ ٻولي (bytecode language) جاوا بائٽ ڪوڊ سان مطابقت نه رکي ٿي ۽ پنھنجي ورچوئل مشين تي ھلندي آھي، گھٽ ميموري ڊيوائسز جھڙوڪ اسمارٽ فونز ۽ ٽيبليٽ ڪمپيوٽرن لاءِ بھتر آھي. اینڊروئڊ ورزن تي مدار رکندي، بائيٽ ڪوڊ يا ته ڊالڪ ورچوئل مشين جي ذريعي تفسير ڪيو ويو آهي يا اینڊروئڊ رن ٽائم پاران اصلي ڪوڊ ۾ مرتب ڪيو ويو آهي. اینڊروئڊ مڪمل جاوا ایس.اي. معياري لائبريري مهيا نٿو ڪري، جيتوڻيڪ اینڊروئڊ ایس.ڊي.ڪي. ۾ ان جي وڏي سب سیٽ جو هڪ آزاد عمل شامل آهي. اهو جاوا 6 ۽ ڪجهه جاوا 7 خاصيتن کي سپورٽ ڪري ٿو، معياري لائبريري (Apache Harmony) سان مطابقت رکندڙ عمل درآمد پيش ڪري ٿو. ===تڪرار=== گوگل انڪارپوریشن، اینڊروئڊ ۾ جاوا سان لاڳاپيل ٽيڪنالاجي جو استعمال اوريڪل انڪارپوریشن ۽ گوگل انڪارپوریشن جي وچ ۾ قانوني تڪرار جو سبب بڻيو. 7 مئي 2012ع تي، هڪ سان فرانسسڪو جيوري معلوم ڪيو ته جيڪڏهن اي.پي.آء (APIs) ڪاپي رائيٽ ٿي سگهي ٿي، ته پوءِ گوگل اینڊروئڊ ڊیوائيسز ۾ جاوا جي استعمال سان اوريڪل جي ڪاپي رائيٽ جي خلاف ورزي ڪئي هئي. ضلعي جج وليم السپ 31 مئي، 2012ع تي فيصلو ڏنو ته اي.پي.آء ڪاپي رائيٽ نٿا ٿي سگهن، پر مئي، 2014ع ۾ آمريڪي عدالت آف اپيلز فار فيڊرل سرڪٽ طرفان ان کي رد ڪيو ويو. 26 مئي، 2016ع تي، ضلعي عدالت گوگل جي حق ۾ فيصلو ڏنو. اینڊروئڊ ۾ جاوا اي.پي.آء جي ڪاپي رائيٽ جي خلاف ورزي جي حڪمراني منصفانه استعمال کي قائم ڪري ٿي. مارچ 2018ع ۾، هي حڪمران اپيل ڪورٽ طرفان رد ڪيو ويو، جنهن سان فرانسسڪو ۾ وفاقي عدالت کي نقصان جي تعين ڪرڻ جو ڪيس موڪليو ويو. گوگل جنوري 2019ع ۾ آمريڪا جي سپريم ڪورٽ ۾ سرٽيوريري جي رٽ لاءِ هڪ درخواست داخل ڪئي ته انهن ٻن حڪمن کي چيلينج ڪرڻ لاءِ جيڪي اپيل ڪورٽ طرفان اوريڪل جي حق ۾ ڪيا ويا. 5 اپريل، 2021ع تي، عدالت گوگل جي حق ۾ 6-2 جو فيصلو ڪيو، ته جاوا اي.پي.آء جي استعمال کي مناسب استعمال سمجهيو وڃي. تنهن هوندي، عدالت اي.پي.آء جي ڪاپي رائيٽ تي حڪمراني ڪرڻ کان انڪار ڪري ڇڏيو، ان جي بدران چونڊ ڪري انهن جي حڪمراني جو تعين ڪرڻ لاءِ، "خالص دليل جي خاطر" جاوا جي اي.پي.آء. ڪاپي رائيٽ قابل غور ڪندي. ==پڻ ڏسو== {{Portal|ڪمپيوٽر پروگرامنگ}} * سي شارپ (#C) پروگرامنگ جي ٻولي * سي ++ (++C) * جاوا APIs جي فهرست * جاوا فريم ورڪ جي فهرست * JVM ٻولين جي فهرست * جاوا ورچوئل مشينن جي فهرست * سي شارپ ۽ جاوا جو موازنو * جاوا ۽ C++ جو موازنو * پروگرامنگ ٻولين جو موازنو ==حوالا== {{حوالا}} ==خارجي لنڪس== * * {{Commons-inline}} * {{Wikibooks-inline|Java Programming}} * [https://discu.eu/weekly/java/ ''Java Weekly''] {{Webarchive|url=https://web.archive.org/web/20240822213928/https://discu.eu/weekly/java/ |date=2024-08-22 }} {{Authority control}} [[زمرو:جاوا (پروگرامنگ ٻولي)|جاوا]] [[زمرو:پروگرامنگ ٻوليون]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر ٻوليون]] [[زمرو:سن مائڪرو سسٽم]] [[زمرو:JVM پروگرامنگ ٻوليون]] [[زمرو:سي پروگرامنگ ٻولي خاندان]] [[زمرو:سي پروگرامنگ ٻولي]] [[زمرو:مرتب ڪيل پروگرامنگ ٻوليون]] [[زمرو:ڪلاس تي ٻڌل پروگرامنگ ٻوليون]] [[زمرو:هم آهنگ پروگرامنگ ٻوليون]] [[زمرو:ملٽي پيراڊائم پروگرامنگ ٻوليون]] [[زمرو:جاوا پليٽ فارم|پروگرامنگ ٻولي]] [[زمرو:1995 ۾ ٺاهيل پروگرامنگ ٻوليون]] [[زمرو:مضمون مثال طور جاوا ڪوڊ]] [[زمرو:جاوا وضاحت جي درخواستون|پروگرامنگ ٻولي]] [[زمرو:جامد ٽائيپ ٿيل پروگرامنگ ٻوليون]] [[زمرو:اعتراض تي مبني پروگرامنگ ٻوليون]] gg4pvjej32iiqykq971w49ye6w3ecq7 14 37020 371810 371786 2026-04-16T19:06:22Z Ibne maryam 17680 371810 wikitext text/x-wiki {{Category diffuse}} {{Infobox library classification |DDC= |LCC= |UDC=0 004}} {{Cat main|ڪمپيوٽر سائنس}} {{Commons category|ڪمپيوٽر سائنس}} * [[ڪمپيوٽر سائنس جي تاريخ]] * [[ڪمپيوٽر سائنس جو خاڪو]] * [[بولين الجبرا]] * [[روبوٽڪس]] * [[ڪمپيوٽر پروگرامنگ]] * [[سافٽ ويئر ڊيزائننگ]] * [[نيٽ ورڪنگ]] [[زمرو:ڪمپيوٽر]] [[زمرو:اطلاقي سائنس]] l62y0fgrobjx329q9krab4gbikh1ohv 0 39349 371809 105296 2026-04-16T18:38:40Z Redaktor GLAM 19451 Higher resolution version of image 371809 wikitext text/x-wiki [[Image:Hamburgerpaumelle.JPG|380px|thumb|A barrel hinge]] '''انجيس'''--- يا-- '''قبضو''' درين ۽ دروازن کي لڳائڻ ۽ انھن اندر مختلف جزن ذريعي ڳانڍاپو رکڻ واسطي ھيٺين قسمن جي قبضن يا انجيسن جي ضرورت پوندي آھي. انجيسون يا قبضا : (Hinges) دروازن ۽ درين جي نوعيت مطابق عام طرح سان ھيٺ ڄاڻايل قسم جون انجيسون استعمال ڪيون وينديون آھن.<br> (i) بُٽ ھنجِس يا ڪتابي انجيسون: (Butt Hingest ھن قسم جون انجيسون عام طرح سان استعمال ڪيون وينديون آھن. انھن جو ھڪ حصو تاڪ جي پاسي ۾ ۽ ٻيو حصو چوڪاٺي جي پاتام ۾ اسڪرن ذريعي لڳايو ويندو آھي. انجيسن لڳائڻ وقت اسڪرن يا پيچن کي ھٿوڙيءَ سان ٺوڪي نھ لڳائجي ڇاڪاڻ تھ ائين ڪرڻ سان ڪجھھ وقت کان پوءِ اھي ڍرا ٿي نڪري ايندا آھن. انھيءَ ڪري انھن کي اسڪرو ڊرائيور يعني پيچ ڪش سان لڳائڻ گھرجي.<br> (ii) ٽي – انجيسون يا پڇر انجيسون: (T- Hinges)<br> ھي ھڪ قسم جو گھاڙو لوھ (Wrought iron) جون فتيلون آھن، ھنن جي ڊگھي ٻانھن وارو حصو تاڪ جي افقيءَ پٽيءَ ۾ اسڪرن سان لڳايو ويندو آھي ۽ ٻيو ڌاتيءَ جي پٽيءَ وارو حصو چوڪاٺي ۾ جڙيو ويندو آھي. ھن قسم جون انجيسون معمولي قسم جي دروازن لاءِ ٺيڪ آھن ۽ کين ڳرن ۽ سٺي قسم جي دروازن ۾ استعمال نھ ڪرڻ گھرجي.<br> (iii) ٻن طرفن واريون انجيسون: (Back flap Hinges) ھن قسم جون ٻھ طرفيون انجيسون اھڙن ھنڌن تي استعمال ڪبيون آھن، جتي اھڙا تہ سنھا تاڪ لڳائبا آھن جو سادين انجيسن جو لڳائڻ ممڪن نہ ھوندو آھي. (iv) ڪوڪن واريون انجيسون: (Pin Hinges) جڏھن تاڪن جو وزن ايترو ڳرو ھوندو آھي جو ٻين قسمن جي انجيسن سان انھن کي نہ لڳائي سگھبو آھي تھ اھڙيءَ حالت ۾ ھن قسم جون ڪلين واريون انجيسون لڳائبيون آھن. <gallery> Image:HingesOldB.jpg|Ancient pivot hinges قديم [[پيوٽ انجيس]]. Image:Hinge2P2.jpg|گھاڙي لوھ wrought iron مان ٺھيل بيرل انجيس. Image:Hinge2P3.jpg| پتل جي ٺھيل پٽيءَ واري بيرل انجيس. Image:Hinge3P.jpg|ٻنھي پاسن کان فٽ ٿيندڙ بٽ انجيس جا منڍا. Image:Topfscharnier.jpg|فرنيچر جي در جو اسپرنگ تالو . Image:Hinge 01.jpg|ڪٽ لڳل يا ڪسيل انجيس. Image:Haar hung doors (99309543).jpg|ٽنگيل در جي انجيس جو هڪ قسم. Image:Mint box polypropylene lid.JPG|دٻي واري انجيس جو هڪ قسم. </gallery> j6s9qjjjifn8an4c9midf51uqgctgty 0 47860 371851 265434 2026-04-16T22:41:41Z Milenioscuro 9642 ([[c:GR|GR]]) [[File:Cantones de Imbabura.png]] → [[File:Mapa de la provincia de Imbabura (político 2020).svg]] svg 371851 wikitext text/x-wiki {{Infobox settlement <!-- See Template:Infobox settlement for additional fields and descriptions --> <!-- Basic info ----------------> |name = امبابورا Imbabura |official_name = امبابورا صوبو<br> Province of Imbabura |other_name = |native_name = |nickname = |settlement_type =صوبو |total_type = |motto = <!-- images and maps -----------> |image_skyline = Imbabura des del sud.JPG |imagesize = |image_caption = [[مائونٽ امبابورا]] نالي ٻرندڙ جبل ملڪ جي ڏکڻ اوڀر ۾ واقع |image_flag = Bandera Provincia Imbabura.svg |flag_size = |image_seal = |seal_size = |image_shield = |shield_size = |image_blank_emblem = |blank_emblem_type = |blank_emblem_size = |image_map = Ecuador Imbabura province.svg |mapsize = |map_caption = ايڪئيڊور جو امبابورا صوبو |image_map1 = Mapa de la provincia de Imbabura (político 2020).svg |mapsize1 = |map_caption1 = امبابورا صوبي جي ڪينٽنن جو نقشو |image_dot_map = |dot_mapsize = |dot_map_caption = |dot_x = |dot_y = |pushpin_map = <!-- the name of a location map as per http://en.wikipedia.org/wiki/Template:Location_map --> |pushpin_label_position = <!-- the position of the pushpin label: left, right, top, bottom, none --> |pushpin_map_caption = |pushpin_mapsize = <!-- Location ------------------> |subdivision_type = ملڪ |subdivision_name = {{ECU}} <!-- Smaller parts (e.g. boroughs of a city) and seat of government --> |seat_type =گاديءَ جو هنڌ |seat = [[ابارا ]] |parts_type = [[ايڪئيڊور جون ڪئنٽنون|ڪئنٽنون]] |parts_style = coll |parts = |p1 = |p2 = |p3 = |p4 = |p5 = |p6 = |p7 = |p8 = <!-- Politics -----------------> |government_footnotes = |government_type = |leader_title = صوبائي [[پريفيڪٽ]] (سربراھ) |leader_name =ڊيئيگو گارشيا (2019) |established_title = قيام |established_date = |established_title1 = قانوني قيام |established_date1 = |named_for = <!-- Area ---------------------> |area_magnitude = |unit_pref = <!--Enter: Imperial, to display imperial before metric--> |area_footnotes = |area_total_km2 = 4587.51 |area_land_km2 = |area_water_km2 = |area_total_sq_mi = |area_land_sq_mi = |area_water_sq_mi = |area_water_percent = <!-- Elevation --------------------------> |elevation_footnotes = |elevation_m = |elevation_ft = |elevation_max_m = |elevation_max_ft = |elevation_min_m = |elevation_min_ft = <!-- Population -----------------------> |population_as_of = 2010 واري آدمشماري |population_footnotes = |population_note = |population_total = 398244 |population_density_km2 = auto |population_density_sq_mi = <!-- General information ---------------> |timezone = [[ايڪئيڊور جو وقت]] |utc_offset = |timezone_DST = |utc_offset_DST = |blank_name_sec2 = [[هيومن ڊويلپمنٽ انڊيڪس|ايڇ ڊي آء]] (2017) |blank_info_sec2 = 0.747<ref>{{Cite web|url=https://es.scribd.com/document/398970547/Indice-de-Desarrollo-Humano-en-Ecuador|title=Human Development Index in Ecuador|access-date=2019-02-05|last=Villalba|first=Juan|website=Scribd|language=es}}</ref> |postal_code_type = |postal_code = |area_code = |registration_plate = I |website = |footnotes = }} '''امبابورا صوبو'''{{ٻيا نالا|انگريزي= ''' Province of Imbabura'''}} ({{IPA-es|imbaˈβuɾa}}) ايڪئيڊور ملڪ جو ھڪ صوبو آهي جنھن جي گادي جو هنڌ [[ابارا]] شھر آھي. ھن صوبي جي ماڻھن جي ٻولي اسپيني ۽ امبابوري ٻولي آھي. مائونٽ امبابورا نالي ٻرندڙ جبل ھن صوبي ۾ واقع آهي. ==انتظامي ورھاست== ھن صوبي ۾ انتظامي ورھاست واري ايڪي کي [[ڪينٽن]] چوندا آھن. صوبو ڇھ ڪينٽنن ۾ ورھايل آھي جيڪي ھيٺ فھرست ۾ 2010 جي ٿيل آدمشماري سميت ظاهر ڪيل آهن.<ref>[http://www.statoids.com/yec.html Cantons of Ecuador]. Statoids.com. Retrieved 4 November 2009.</ref> {| class="wikitable sortable" ! ڪينٽن !! آبادي (2001) !! آبادي (2010) !!ايراضي (km²) !! صدر مقام |- | [[انتونيو اينٽي ڪينٽن|انتونيو]] || align=right|36,053 || align=right|43,518 || align=right|81 || [[اٽونٽاڪي]] |- | [[ڪوٽاڪاچي ڪينٽن|ڪوٽاڪاچي]] || align=right|37,215 || align=right|40,036 || align=right|1,726 || [[ڪوٽاڪاچي (شھر)]] |- | [[ابارا ڪينٽن|ابارا]] || align=right|153,256 || align=right|181,175 || align=right|1,093 || [[ابارا، ايڪئيڊور|ابارا]] |- | [[اوٽاوالو ڪينٽن|اوٽاوالو]] || align=right|90,188 || align=right|104,874 || align=right|500 || [[اوٽاوالو (شھر) ]] |- | [[پماپيرو ڪينٽن |پماپيرو ]] || align=right|12,951 || align=right|12,970 || align=right|437 || [[پماپيرو (شھر) ]] |- | [[سان مگل ڊي ارڪوڪي ڪينٽن|سان مگل ڊي ارڪوڪي]] || align=right|14,381 ||align=right|15,671 || align=right|779 || [[ارڪوڪي]] |} [[فائل:Cotacachi volcano.JPG|thumb|left|250px|ڪوٽاڪاچي نالي ٻرندڙ جبل جو امبابورا جي ڪوٽاڪاچي شھر وٽان ھڪ منظر ]] == حوالا == == حوالا == {{حوالا}} [[زمرو:ايڪواڊور جا صوبا]] ao2obok0rqqu50ab4p8rpy6cujpuigq 14 78147 371857 371776 2026-04-17T06:42:20Z Ibne maryam 17680 371857 wikitext text/x-wiki {{اصل مضمون}} {{زمرو ڪامنز}} [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:سافٽ ويئر انجنيئرڱ]] [[زمرو:ڪمپيوٽر سافٽ ويئر]] [[زمرو:ڪمپيوٽر سائنس جون ذيلي شاخون]] hc4923z3hw7w7os7f2tike4dbtas4ce 0 81512 371845 340145 2026-04-16T20:58:48Z Ibne maryam 17680 371845 wikitext text/x-wiki {{short description|Electronic engineering involved in the design of electronic circuits, devices, and their systems}} {{Distinguish|اليڪٽريڪل انجنيئرنگ}} [[Image:Silego clock generator.JPG|thumb|right|پرنٽڊ سرڪٽ بورڊ ]] [[File:Electrical Circuit with an IC.jpg|thumb|برقي سرڪٽ هڪ انٽيگرئٽيڊ سرڪٽ (IC) جي گڏ ]] '''اليڪٽرونڪ انجنيئرنگ''' <small>(Electronic Engineering)</small> [[بجلي جي انجنيئرنگ|اليڪٽريڪل انجنيئرنگ]] جو هڪ ذيلي نظم آهي جيڪو 20هين صدي جي شروعات ۾ ظاهر ٿيو ۽ فعال اجزاء، جهڙوڪ [[اليڪٽرڪ چارج|برقي ڪرنٽ]] جي وهڪري کي وڌائڻ ۽ ڪنٽرول ڪرڻ لاءِ، [[سيمي ڪنڊڪٽر]] ڊوائيسز جي اضافي استعمال سان ممتاز ڪيو ويو آهي. اڳي اليڪٽريڪل انجنيئرنگ صرف غير فعال ڊوائيسز، جهڙوڪ مڪينيڪل سوئچ، رزسٽر، انڊڪٽرز ۽ ڪيپيسيٽر، استعمال ڪندا هئا. اهو شعبو ذيلي شعبن، جهڙوڪ اينالاگ اليڪٽرانڪس، ڊيجيٽل اليڪٽرانڪس، صارف اليڪٽرانڪس، ايمبيڊڊ سسٽم ۽ پاور اليڪٽرانڪس، تي پکڙيل آهي. اهو ڪيترن ئي لاڳاپيل شعبن، مثال طور سولڊ اسٽيٽ فزڪس، ٽيلي ڪميونيڪيشن، ريڊيو انجنيئرنگ، ڪنٽرول سسٽم، سگنل پروسيسنگ، سسٽم انجنيئرنگ، ڪمپيوٽر انجنيئرنگ، اوزار انجنيئرنگ، اليڪٽرڪ پاور ڪنٽرول، فوٽونڪس ۽ روبوٽڪس، ۾ پڻ شامل آهي. انسٽيٽيوٽ آف اليڪٽريڪل ۽ اليڪٽرانڪس انجنيئرز (IEEE) آمريڪا ۾ اليڪٽرانڪس انجنيئرن لاءِ سڀ کان اهم پيشه ورانه ادارو آهي؛ برطانيه ۾ برابري وارو ادارو انسٽيٽيوٽ آف انجنيئرنگ اينڊ ٽيڪنالاجي (IET) آهي. بين الاقوامي اليڪٽروٽيڪنيڪل ڪميشن (IEC) اليڪٽريڪل معيار شايع ڪري ٿو جن ۾ اليڪٽرانڪ انجنيئرنگ پڻ شامل آهن. ==تاريخ ۽ ترقي== ==ماهرن جا علائقا== ==تعليم ۽ تربيت== ==پيشه ورانه ادارا== ==پروجيڪٽ انجنيئرنگ== ==پڻ ڏسو== [[:باب:طرزيات|باب:ٽيڪنالاجي]] ==ٻاهريان ڳنڍڻا== {{Sister project links|زمرو:اليڪٽرانڪس }} [[Category:Electronic engineering| ]] [[Category:Electrical engineering]] [[Category:Computer engineering]] [[Category:Engineering disciplines]] ==حوالا== {{حوالا}} [[زمرو:اليڪٽرونڪس انجنيئرنگ]] [[زمرو:انجنيئرنگ]] [[زمرو:برقيات]] [[زمرو:ڪمپيوٽر انجنيئرنگ]] [[زمرو:اليڪٽريڪل انجنيئرنگ]] s7as8sqa5fk6j1mujkxp2t3ef4h7gfa 3 87842 371865 346115 2026-04-17T10:03:07Z Cabayi 4463 Cabayi [[واپرائيندڙ بحث:TobiasEkwueme]] صفحي کي [[واپرائيندڙ بحث:Renamed user 538457f34a28cd5bbb4c5eef5c25ddab]] ڏانھن چوريو سواءِ ڪو ريڊائريڪٽ ڇڏيندي: Automatically moved page while renaming the user "[[Special:CentralAuth/TobiasEkwueme|TobiasEkwueme]]" to "[[Special:CentralAuth/Renamed user 538457f34a28cd5bbb4c5eef5c25ddab|Renamed user 538457f34a28cd5bbb4c5eef5c25ddab]]" 345559 wikitext text/x-wiki {{سانچو:سماجي ڳنڍڻن تي سنڌي وڪيپيڊيا}} <div style="padding:5px;font-size:medium"><center style="word-spacing:1ex">[[Wikipedia:سفارتخانو|سفارتخاني جي صفحي تي پنھنجون سفارشون ڏيو]] </center></div> {| bgcolor="#ADDFAD" align=center style="width:100% !important; -moz-border-radius: 1em;-webkit-border-radius:1em;border-radius:1em; border-top:2px dashed #3eb2c9;border-bottom:2px dashed #3eb2c9;padding: 5px 20px 25px;" |<span style="font-family:MB Lateefi;float:left">'''[[Wikipedia:سفارتخانو|سفارتخانو]]'''</span> <div class="tabber horizTabBox" style="width: 100% !important;"> [[عڪس:Wikipedia laurier wp.png|left|200px]] <center><big>'''بزمِ سنڌي وڪيپيڊيا ۾ ڀلي ڪري آيا''' ''{{PAGENAME}}'''</big></center>'' '''السلام عليڪم! اسان اميد ڪريون ٿا تہ توھان سنڌي وڪيپيڊيا جي لاء بھترين اضافو ثابت ٿيندئو'''.<br> * وڪيپيڊيا ھڪ کليل ڄاڻ چيڪلو آھي جنھن کي اسان سڀ ملي ڪري لکندا ۽ سنواريندا آھيون. وڪيپيڊيا منصوبي جي شروعات جنوري 2001ع ۾ ٿي، جڏھن تہ سنڌي وڪيپيڊيا فيبروري 2006ع ۾ عمل آئي. في الحال ھن وڪيپيڊيا ۾ '''{{NUMBEROFARTICLES}}''' [[Special:Allpages|مضمون]] موجود آھن.<br /> * ھن چيڪلي (انسائيڪلوپيڊيا) ۾ توھان مضمون نويسي، سنوار ۽ تصحيح کان پھريان ھيٺين صفحن تي ضرور نظر وجھو.''' * صفحن جي ظاھريت جي تبديلي ۽ طریقيڪار جي لاءِ ڏسو '''[[خاص:ترجيحات|ترجيحون]]'''. <Font - size=4> '''اصول ۽ قاعدا''' </Font - size> <Font - size=3> '''توھان جو واپرائيندڙ ۽ بحث صفحو''' </Font - size><br> ھتي توھانجو [[خاص:Mypage|'''مخصوص واپرائيندڙ صفحو بہ ھوندو''']] جتي توھان [[:زمرو:يوزر سانچا|پنھنجو تعارف لکي سگھو ٿا]]، ۽ توهانجي [[خاص:Mytalk|واپرائيندڙ بحث]] تي ٻيا رڪنَ توھان سان رابطو ڪري سگھن ٿا ۽ توھان ڏي پيغام موڪلي سگھن ٿا. * '''ڪنھن ٻئي رڪن کي پيغام موڪلڻ وقت ھنن امرن جو خاص خيال رکو''': ** '''جيڪڏھن ضرورت هجي تہ پيغام کي عنوان ضرور ڏيو'''. ** '''پيغام جي آخر ۾ پنهنجي صحيح ضرور وجھو، ان جي لاءِ هي علامت درج ڪريو'''--&#126;&#126;&#126;&#126;''' يا ھن ([[عڪس:Insert-signature.png|link=]]) بٽڻ تي ٽڙڪ ڪريو'''. ** '''[[Wikipedia:اصول بحث|اظھار بحث جي آدابن]] جو خصوصي خيال رکو'''. <Font - size=3> '''تعاون''' </Font - size> * '''وڪيپيڊيا جي ڪنھن بہ صفحي جي سڄي پاسي ڳوليو جو خانو نظر ايندو آھي. جنھن موضوع تي مضمون ٺاھڻ چاھيو تہ ڳوليو جي خاني ۾ لکو، ۽ ڳوليو تي ٽڙڪ ڪريو'''. <inputbox>type=search</inputbox> * '''توھان جي موضوع سان ملندڙ جلندڙ صفحا نظر ايندا. اھو اطمينان ڪرڻ کان پوء تہ توھان جي گهربل موضوع تي پھريان کان مضمون موجود ناھي، توھان نئون صفحو ٺاھي سگھو ٿا واضع هجي تہ ھڪ موضوع تي ھڪ کان وڌيڪ مضمون ٺاھڻ جي اجازت ناھي. توھان ھيٺ ڏنل خانو بہ استعمال ڪري سگھو ٿا'''. <inputbox>type=create</inputbox> * '''لکڻ کان پهرئين ھن ڳالھ جو يقين ڪريو تہ جنھن عنوان تي توھان لکي رھيا آھيو ان تي يا ان سان ملندڙ عنوانن تي وڪي ۾ ڪوئي مضمون نہ ھجي. ان جي لاء توھان ڳوليو جي خاني ۾ عنوان ۽ ان جا هم معنيٰ لفظ (اهڙا لفظ جن جي معني هڪ هجي) لکي ڳولا ڪريو'''.</center> |} -- توھان جي مدد جي لاء ھر وقت حاضر، اوهان جو خادم --[[واپرائيندڙ:KaleemBot|KaleemBot]] ([[واپرائيندڙ بحث:KaleemBot|ڳالھ]]) 10:42, 29 ڊسمبر 2025 ( يو.ٽي.سي) qatw9duarxubupyrjt27g48yfam6hn6 0 90623 371800 368899 2026-04-16T12:32:51Z Memon2025 21315 371800 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' (روسي: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، روس ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ ڪيسپين سمنڊ ۾ وهندو آهي. وولگا جي ڊيگهه 3,531 ڪلوميٽر (2,194 ميل) آهي ۽ ان جو ڪيچمينٽ ايريا 13,60,000 چورس ڪلوميٽر (5,30,000 چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، 8,000 ۽ 8,500 ڪيوبڪ ميٽر (2,80,000 ۽ 3,00,000 ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي روس جي قومي درياهه طور وڏي پيماني تي سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن، ٻيلن جي ميدانن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، ماسڪو سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاڪ لفظ "vòlga" 'گندو، نمي' مان نڪتل آهي. جيڪو ڪيترين ئي سلاواڪ ٻولين ۾ محفوظ آهي. وولگا (влага). نمي. بلغاريا. سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها. نمي. وولگا جو سٿين نالو "راها", لفظي معنيٰ 'گندو' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب آهي "گندو" يا "نمي". هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رʾڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رسا). شبنم، مائع، رس. افسانوي درياهه. جيڪو سنڌو درياهه جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ هيروڊوٽس وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]][[Saratov Bridge]] by night, [[Saratov Oblast]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912upper Volga in the vicinity of [[Staritsa (town), Tver Oblast|Staritsa]], 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظاروthe [[Volga Delta]] from the [[International Space Station]]]] The [[Saratov Bridge]] by night, [[Saratov Oblast]] * The upper Volga in the vicinity of [[Staritsa (town), Tver Oblast|Staritsa]], 1912]] * View of the [[Volga Delta]] from the [[International Space Station]]]] * * * وولگا يورپ جو سڀ کان ڊگهو درياهه آهي. ۽ ان جو ڪيچمينٽ علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو ٽور اوبلاست ۾ وولگوورخووي ڳوٺ ۾ آهي. ماسڪو جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ سينٽ پيٽرسبرگ کان تقريباً 320 ڪلوميٽر (200 ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو. يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي. ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. * وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون (جيڪو لڳ ڀڳ 1,350,000 چورس ڪلوميٽر (520,000 چورس ميل) جي ايراضيءَ مان وهي ٿو). اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي. ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه. اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. * وولگا مغربي روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال. ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي. * زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار. ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. * سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين): The Volga is the longest [[river]] in [[Europe]], and its catchment area is almost entirely inside [[Russia]], though the longest river in Russia is the [[Ob river|Ob]]–[[Irtysh river]] system.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> It belongs to the [[Endorheic basin|closed basin]] of the [[Caspian Sea]], being the longest river to flow into a closed basin. The source of the Volga lies in the village of Volgoverkhov'e in [[Tver Oblast]]. Rising in the [[Valdai Hills]] {{convert|225|m|ft|abbr=on}} [[Above mean sea level|above sea level]] northwest of [[Moscow]] and about {{convert|320|km|mi|abbr=on}} southeast of [[Saint Petersburg]], the Volga heads east past [[Lake Sterzh]], [[Tver]], [[Dubna]], [[Rybinsk]], [[Yaroslavl]], [[Nizhny Novgorod]], and [[Kazan]]. From there it turns south, flows past [[Ulyanovsk]], [[Tolyatti]], [[Samara, Russia|Samara]], [[Saratov]] and [[Volgograd]], and discharges into the Caspian Sea below [[Astrakhan]] at {{convert|28|m|ft|abbr=on}} below sea level.<ref name="readersnatural" /> The Volga has many [[tributaries]], most importantly the [[Kama (river)|Kama]], the [[Oka River|Oka]], the [[Vetluga (river)|Vetluga]], and the [[Sura (river)|Sura]]. The Volga and its tributaries form the Volga river system, which flows through an area of about {{convert|1350000|km2|abbr=on}} in the most heavily populated part of Russia.<ref name="readersnatural" /> The [[Volga Delta]] has a length of about {{convert|160|km|abbr=on}} and includes as many as 500 channels and smaller rivers. The largest [[estuary]] in Europe, it is the only place in Russia where [[pelican]]s, [[flamingo]]s, and [[Nelumbo nucifera|lotus]]es may be found.{{citation needed|date=July 2016}} The Volga freezes for most of its length for three months each year.<ref name="readersnatural" /> The Volga drains most of [[Western Russia]]. Its many large reservoirs provide [[irrigation]] and [[hydroelectric]] power. The [[Moscow Canal]], the [[Volga–Don Canal]], and the [[Volga–Baltic Waterway]] form navigable [[waterway]]s connecting Moscow to the [[White Sea]], the [[Baltic Sea]], the Caspian Sea, the [[Sea of Azov]] and the [[Black Sea]]. High levels of chemical [[pollution]] have adversely affected the river and its habitats. The fertile river valley provides large quantities of [[wheat]] and other agricultural produce, and also has many mineral riches. A substantial petroleum industry centers on the Volga valley. Other resources include [[natural gas]], [[salt]], and [[potash]]. The Volga Delta and the Caspian Sea are [[fishing grounds]]. ===Confluences (downstream to upstream)=== [[File:Tver dusk 3.jpg|thumb|The Starovolzhsky Bridge in [[Tver]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|[[Volga Hydroelectric Station]]]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|The confluence of the Oka (''to the left'') and the Volga in Nizhny Novgorod]] {{colbegin}} * [[Akhtuba]] (near [[Volzhsky, Volgograd Oblast|Volzhsky]]), a [[distributary]] * [[Bolshoy Irgiz]] (near [[Volsk]]) * [[Samara (Volga)|Samara]] (in [[Samara]]) * [[Kama (river)|Kama]] (south of [[Kazan]])<!-- in the Middle Age it was believed to be an origin of the Volga (Itil) – believed by who? surely not by Russians --> * [[Kazanka (river)|Kazanka]] (in Kazan) * [[Sviyaga]] (west of Kazan) * [[Vetluga (river)|Vetluga]] (near [[Kozmodemyansk]]) * [[Sura (river)|Sura]] (in [[Vasilsursk]]) * [[Kerzhenets]] (near [[Lyskovo]]) * [[Oka (river)|Oka]] (in [[Nizhny Novgorod]]) * [[Uzola]] (near [[Balakhna]]) * [[Unzha]] (near [[Yuryevets, Ivanovo Oblast|Yuryevets]]) * [[Kostroma (river)|Kostroma]] (in [[Kostroma]]) * [[Kotorosl]] (in [[Yaroslavl]]) * [[Sheksna]] (in [[Cherepovets]]) * [[Mologa (river)|Mologa]] (near [[Vesyegonsk]]) * [[Kashinka]] (near [[Kalyazin]]) * [[Nerl (Volga)|Nerl]] (near Kalyazin) * [[Medveditsa (Volga)|Medveditsa]] (near [[Kimry]]) * [[Dubna (Volga)|Dubna]] (in [[Dubna]]) * [[Shosha (river)|Shosha]] (near [[Konakovo]]) * [[Tvertsa]] (in [[Tver]]) * [[Vazuza]] (in [[Zubtsov]]) * [[Selizharovka]] (in [[Selizharovo]]) {{colend}} ===Reservoirs (downstream to upstream)=== A number of large hydroelectric reservoirs were constructed on the Volga during the [[Soviet Union|Soviet era]]. They are: * [[Volgograd Reservoir]] * [[Saratov Reservoir]] * [[Kuybyshev Reservoir]]{{spaced ndash}} the largest in Europe by surface * [[Cheboksary Reservoir]] * [[Gorky Reservoir]] * [[Rybinsk Reservoir]] * [[Uglich Reservoir]] * [[Ivankovo Reservoir]] ===Biggest cities on the shores of the Volga=== * [[Kazan]] * [[Nizhny Novgorod]] * [[Samara]] * [[Volgograd]] * [[Saratov]] * [[Tolyatti]] * [[Yaroslavl]] * [[Astrakhan]] * [[Ulyanovsk]] * [[Cheboksary]] * [[Tver]] ===Bridges across the Volga=== * [[Kostroma rail bridge]] ===Human history=== [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] kmbsmcqgfri93va388otazbz3w7k5j9 371801 371800 2026-04-16T12:45:36Z Memon2025 21315 371801 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' (روسي: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، روس ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ ڪيسپين سمنڊ ۾ وهندو آهي. وولگا جي ڊيگهه 3,531 ڪلوميٽر (2,194 ميل) آهي ۽ ان جو ڪيچمينٽ ايريا 13,60,000 چورس ڪلوميٽر (5,30,000 چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، 8,000 ۽ 8,500 ڪيوبڪ ميٽر (2,80,000 ۽ 3,00,000 ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي روس جي قومي درياهه طور وڏي پيماني تي سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن، ٻيلن جي ميدانن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، ماسڪو سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاڪ لفظ "vòlga" 'گندو، نمي' مان نڪتل آهي. جيڪو ڪيترين ئي سلاواڪ ٻولين ۾ محفوظ آهي. وولگا (влага). نمي. بلغاريا. سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها. نمي. وولگا جو سٿين نالو "راها", لفظي معنيٰ 'گندو' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب آهي "گندو" يا "نمي". هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رʾڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رسا). شبنم، مائع، رس. افسانوي درياهه. جيڪو سنڌو درياهه جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ هيروڊوٽس وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|The Starovolzhsky Bridge in [[Tver]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|[[Volga Hydroelectric Station]]]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|The confluence of the Oka (''to the left'') and the Volga in Nizhny Novgorod]] {{colbegin}} * [[Akhtuba]] (near [[Volzhsky, Volgograd Oblast|Volzhsky]]), a [[distributary]] * [[Bolshoy Irgiz]] (near [[Volsk]]) * [[Samara (Volga)|Samara]] (in [[Samara]]) * [[Kama (river)|Kama]] (south of [[Kazan]])<!-- in the Middle Age it was believed to be an origin of the Volga (Itil) – believed by who? surely not by Russians --> * [[Kazanka (river)|Kazanka]] (in Kazan) * [[Sviyaga]] (west of Kazan) * [[Vetluga (river)|Vetluga]] (near [[Kozmodemyansk]]) * [[Sura (river)|Sura]] (in [[Vasilsursk]]) * [[Kerzhenets]] (near [[Lyskovo]]) * [[Oka (river)|Oka]] (in [[Nizhny Novgorod]]) * [[Uzola]] (near [[Balakhna]]) * [[Unzha]] (near [[Yuryevets, Ivanovo Oblast|Yuryevets]]) * [[Kostroma (river)|Kostroma]] (in [[Kostroma]]) * [[Kotorosl]] (in [[Yaroslavl]]) * [[Sheksna]] (in [[Cherepovets]]) * [[Mologa (river)|Mologa]] (near [[Vesyegonsk]]) * [[Kashinka]] (near [[Kalyazin]]) * [[Nerl (Volga)|Nerl]] (near Kalyazin) * [[Medveditsa (Volga)|Medveditsa]] (near [[Kimry]]) * [[Dubna (Volga)|Dubna]] (in [[Dubna]]) * [[Shosha (river)|Shosha]] (near [[Konakovo]]) * [[Tvertsa]] (in [[Tver]]) * [[Vazuza]] (in [[Zubtsov]]) * [[Selizharovka]] (in [[Selizharovo]]) {{colend}} ===Reservoirs (downstream to upstream)=== A number of large hydroelectric reservoirs were constructed on the Volga during the [[Soviet Union|Soviet era]]. They are: * [[Volgograd Reservoir]] * [[Saratov Reservoir]] * [[Kuybyshev Reservoir]]{{spaced ndash}} the largest in Europe by surface * [[Cheboksary Reservoir]] * [[Gorky Reservoir]] * [[Rybinsk Reservoir]] * [[Uglich Reservoir]] * [[Ivankovo Reservoir]] ===Biggest cities on the shores of the Volga=== * [[Kazan]] * [[Nizhny Novgorod]] * [[Samara]] * [[Volgograd]] * [[Saratov]] * [[Tolyatti]] * [[Yaroslavl]] * [[Astrakhan]] * [[Ulyanovsk]] * [[Cheboksary]] * [[Tver]] ===Bridges across the Volga=== * [[Kostroma rail bridge]] ===Human history=== [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] ffg3bnwjuqd5cu7dhhn59ebg18k41ho 371802 371801 2026-04-16T15:00:08Z Memon2025 21315 371802 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' (روسي: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، روس ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ ڪيسپين سمنڊ ۾ وهندو آهي. وولگا جي ڊيگهه 3,531 ڪلوميٽر (2,194 ميل) آهي ۽ ان جو ڪيچمينٽ ايريا 13,60,000 چورس ڪلوميٽر (5,30,000 چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، 8,000 ۽ 8,500 ڪيوبڪ ميٽر (2,80,000 ۽ 3,00,000 ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي روس جي قومي درياهه طور وڏي پيماني تي سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن، ٻيلن جي ميدانن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، ماسڪو سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاڪ لفظ "vòlga" 'گندو، نمي' مان نڪتل آهي. جيڪو ڪيترين ئي سلاواڪ ٻولين ۾ محفوظ آهي. وولگا (влага). نمي. بلغاريا. سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها. نمي. وولگا جو سٿين نالو "راها", لفظي معنيٰ 'گندو' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب آهي "گندو" يا "نمي". هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رʾڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رسا). شبنم، مائع، رس. افسانوي درياهه. جيڪو سنڌو درياهه جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ هيروڊوٽس وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|اسٽاروووزسڪي پل - [[ٽوير اوبلاسٽ|ٽوير اوبلاست]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|وولگا هائيڊرو اليڪٽرڪ اسٽيشن]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|[[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾ اوڪا (کاٻي پاسي) ۽ وولگا جو سنگم]] * اختبو. (Volar. zisky جي ويجهو)، هڪ تقسيم ڪندڙ * بالشوائي. ارجيز. (Volsk جي ويجهو) * سمارا ([[سمارا اوبلاسٽ|سامارا اوبلاست]] ۾) * ڪاما (ڪازان جي ڏکڻ) * قازانڪا (قازان ۾) * سوويگا (اولهه قازان) * ويٽ. luga (ڪوزموڊيميانسڪ جي ويجهو) * سورا (واسيلسرسڪ ۾) * کير. zhenets (Lyskovo جي ويجهو) * اوکا (نزني نوگوروڊ ۾) * ازولا (بلخنا جي ويجهو) * اونڌا. (Yurevets جي ويجهو) * ڪوسٽروما. (ڪوسٽروما ۾) * ڪوٽوروسل (ياروسلاو ۾) * شيڪسينا (چيريپو ويٽس ۾) * Mologa (Vesegonsk جي ويجهو) * ڪاشينڪا (ڪليزين جي ويجهو) * نيرل (ڪليزين جي ويجهو) * Medveditsa (ڪيمري جي ويجهو) * ڊبنا (ڊبنا ۾) * شوشا (Konakovo جي ويجهو) * Tvertsa (Tver ۾) * Vazuza (Zubtsov ۾) * Selizharovka (Selizharovo ۾) ==== آبي ذخيرا (لاڙ کان مٿي تائين) ==== * سوويت دور ۾ وولگا تي ڪيترائي وڏا هائيڊرو اليڪٽرڪ ذخيرا تعمير ڪيا ويا. اهي آهن: * وولگوگراڊ ذخيرو * ساراٽوف ذخيرو * ڪوئبيشيف ذخيرو - مٿاڇري جي لحاظ کان يورپ ۾ سڀ کان وڏو * چيبوڪسري ذخيرو * گورڪي ذخيرو * ريبنسک ذخيرو * يوگليچ ذخيرو * ايوانڪوو ذخيرو ==== وولگا جي ڪنارن تي سڀ کان وڏا شهر ==== * قازان * نزني نووگوروڊ * سمارا * وولگوگراڊ * سراتوف * ٽولياٽِي * ياروسلاوِل * آسٽراخان * اوليانووسک * چيبوڪسري * ٽيور ==== وولگا جي پار پل ==== * ڪوسٽروما ريل پل === انساني تاريخ === [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] 03dm780zw1n79v3agta1338nh955lym 371803 371802 2026-04-16T15:16:54Z Memon2025 21315 371803 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' ([[روسي ٻولي|روسي]]: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، [[روس]] ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ [[ڪيسپئن سمنڊ|ڪيسپين سمنڊ]] ۾ وهندو آهي. وولگا جي ڊيگهه <small>3,531</small> ڪلوميٽر (<small>2,194</small> ميل) آهي ۽ ان جو ڪيچمينٽ ايريا <small>13,60,000</small> چورس ڪلوميٽر (<small>5,30,000</small> چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، <small>8,000</small> ۽ <small>8,500</small> ڪيوبڪ ميٽر (<small>2,80,000</small> ۽ <small>3,00,000</small> ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي وڏي پيماني تي روس جي قومي درياهه طور سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، [[ماسڪو]] سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا [[ڪيسپئن سمنڊ|ڪئسپين سمنڊ]] ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاڪ لفظ "vòlga" 'گندو، نمي' مان نڪتل آهي. جيڪو ڪيترين ئي سلاواڪ ٻولين ۾ محفوظ آهي. وولگا (влага). نمي. بلغاريا. سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها. نمي. وولگا جو سٿين نالو "راها", لفظي معنيٰ 'گندو' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب آهي "گندو" يا "نمي". هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رʾڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رسا). شبنم، مائع، رس. افسانوي درياهه. جيڪو سنڌو درياهه جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ هيروڊوٽس وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|اسٽاروووزسڪي پل - [[ٽوير اوبلاسٽ|ٽوير اوبلاست]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|وولگا هائيڊرو اليڪٽرڪ اسٽيشن]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|[[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾ اوڪا (کاٻي پاسي) ۽ وولگا جو سنگم]] * اختبو. (Volar. zisky جي ويجهو)، هڪ تقسيم ڪندڙ * بالشوائي. ارجيز. (Volsk جي ويجهو) * سمارا ([[سمارا اوبلاسٽ|سامارا اوبلاست]] ۾) * ڪاما (ڪازان جي ڏکڻ) * قازانڪا (قازان ۾) * سوويگا (اولهه قازان) * ويٽ. luga (ڪوزموڊيميانسڪ جي ويجهو) * سورا (واسيلسرسڪ ۾) * کير. zhenets (Lyskovo جي ويجهو) * اوکا (نزني نوگوروڊ ۾) * ازولا (بلخنا جي ويجهو) * اونڌا. (Yurevets جي ويجهو) * ڪوسٽروما. (ڪوسٽروما ۾) * ڪوٽوروسل (ياروسلاو ۾) * شيڪسينا (چيريپو ويٽس ۾) * Mologa (Vesegonsk جي ويجهو) * ڪاشينڪا (ڪليزين جي ويجهو) * نيرل (ڪليزين جي ويجهو) * Medveditsa (ڪيمري جي ويجهو) * ڊبنا (ڊبنا ۾) * شوشا (Konakovo جي ويجهو) * Tvertsa (Tver ۾) * Vazuza (Zubtsov ۾) * Selizharovka (Selizharovo ۾) ==== آبي ذخيرا (لاڙ کان مٿي تائين) ==== * سوويت دور ۾ وولگا تي ڪيترائي وڏا هائيڊرو اليڪٽرڪ ذخيرا تعمير ڪيا ويا. اهي آهن: * وولگوگراڊ ذخيرو * ساراٽوف ذخيرو * ڪوئبيشيف ذخيرو - مٿاڇري جي لحاظ کان يورپ ۾ سڀ کان وڏو * چيبوڪسري ذخيرو * گورڪي ذخيرو * ريبنسک ذخيرو * يوگليچ ذخيرو * ايوانڪوو ذخيرو ==== وولگا جي ڪنارن تي سڀ کان وڏا شهر ==== * قازان * نزني نووگوروڊ * سمارا * وولگوگراڊ * سراتوف * ٽولياٽِي * ياروسلاوِل * آسٽراخان * اوليانووسک * چيبوڪسري * ٽيور ==== وولگا جي پار پل ==== * ڪوسٽروما ريل پل === انساني تاريخ === [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] orltma45swmp4qsinga6p4xr5w7jnqp 371804 371803 2026-04-16T15:23:25Z Memon2025 21315 371804 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' ([[روسي ٻولي|روسي]]: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، [[روس]] ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ [[ڪيسپئن سمنڊ|ڪيسپين سمنڊ]] ۾ وهندو آهي. وولگا جي ڊيگهه <small>3,531</small> ڪلوميٽر (<small>2,194</small> ميل) آهي ۽ ان جو ڪيچمينٽ ايريا <small>13,60,000</small> چورس ڪلوميٽر (<small>5,30,000</small> چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، <small>8,000</small> ۽ <small>8,500</small> ڪيوبڪ ميٽر (<small>2,80,000</small> ۽ <small>3,00,000</small> ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي وڏي پيماني تي روس جي قومي درياهه طور سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، [[ماسڪو]] سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا [[ڪيسپئن سمنڊ|ڪئسپين سمنڊ]] ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاوڪ لفظ "vòlga" 'نم' مان نڪتل آهي. جيڪو ڪيترين ئي سلاوڪ ٻولين ۾ محفوظ آهي. وولگا (влага, نمي; بلغاريا; سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها "نمي) وولگا جو سٿين نالو "راها", لفظي معنيٰ 'نم' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب "نم" آهي. هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رس). شبنم، مائع، رس. افسانوي درياهه. جيڪو [[سنڌو درياھ|سنڌو درياهه]] جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ [[هيروڊوٽس]] وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|اسٽاروووزسڪي پل - [[ٽوير اوبلاسٽ|ٽوير اوبلاست]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|وولگا هائيڊرو اليڪٽرڪ اسٽيشن]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|[[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾ اوڪا (کاٻي پاسي) ۽ وولگا جو سنگم]] * اختبو. (Volar. zisky جي ويجهو)، هڪ تقسيم ڪندڙ * بالشوائي. ارجيز. (Volsk جي ويجهو) * سمارا ([[سمارا اوبلاسٽ|سامارا اوبلاست]] ۾) * ڪاما (ڪازان جي ڏکڻ) * قازانڪا (قازان ۾) * سوويگا (اولهه قازان) * ويٽ. luga (ڪوزموڊيميانسڪ جي ويجهو) * سورا (واسيلسرسڪ ۾) * کير. zhenets (Lyskovo جي ويجهو) * اوکا (نزني نوگوروڊ ۾) * ازولا (بلخنا جي ويجهو) * اونڌا. (Yurevets جي ويجهو) * ڪوسٽروما. (ڪوسٽروما ۾) * ڪوٽوروسل (ياروسلاو ۾) * شيڪسينا (چيريپو ويٽس ۾) * Mologa (Vesegonsk جي ويجهو) * ڪاشينڪا (ڪليزين جي ويجهو) * نيرل (ڪليزين جي ويجهو) * Medveditsa (ڪيمري جي ويجهو) * ڊبنا (ڊبنا ۾) * شوشا (Konakovo جي ويجهو) * Tvertsa (Tver ۾) * Vazuza (Zubtsov ۾) * Selizharovka (Selizharovo ۾) ==== آبي ذخيرا (لاڙ کان مٿي تائين) ==== * سوويت دور ۾ وولگا تي ڪيترائي وڏا هائيڊرو اليڪٽرڪ ذخيرا تعمير ڪيا ويا. اهي آهن: * وولگوگراڊ ذخيرو * ساراٽوف ذخيرو * ڪوئبيشيف ذخيرو - مٿاڇري جي لحاظ کان يورپ ۾ سڀ کان وڏو * چيبوڪسري ذخيرو * گورڪي ذخيرو * ريبنسک ذخيرو * يوگليچ ذخيرو * ايوانڪوو ذخيرو ==== وولگا جي ڪنارن تي سڀ کان وڏا شهر ==== * قازان * نزني نووگوروڊ * سمارا * وولگوگراڊ * سراتوف * ٽولياٽِي * ياروسلاوِل * آسٽراخان * اوليانووسک * چيبوڪسري * ٽيور ==== وولگا جي پار پل ==== * ڪوسٽروما ريل پل === انساني تاريخ === [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] 94wtj9t01tqohlhfk3qbeogv4hy65qy 371862 371804 2026-04-17T09:06:09Z Memon2025 21315 371862 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' ([[روسي ٻولي|روسي]]: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، [[روس]] ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ [[ڪيسپئن سمنڊ|ڪيسپين سمنڊ]] ۾ وهندو آهي. وولگا جي ڊيگهه <small>3,531</small> ڪلوميٽر (<small>2,194</small> ميل) آهي ۽ ان جو ڪيچمينٽ ايريا <small>13,60,000</small> چورس ڪلوميٽر (<small>5,30,000</small> چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، <small>8,000</small> ۽ <small>8,500</small> ڪيوبڪ ميٽر (<small>2,80,000</small> ۽ <small>3,00,000</small> ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي وڏي پيماني تي روس جي قومي درياهه طور سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، [[ماسڪو]] سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا [[ڪيسپئن سمنڊ|ڪئسپين سمنڊ]] ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاوڪ لفظ "vòlga" 'نم' مان نڪتل آهي. جيڪو ڪيترين ئي سلاوڪ ٻولين ۾ محفوظ آهي. وولگا (влага, نمي; بلغاريا; سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها "نمي) وولگا جو سٿين نالو "راها", لفظي معنيٰ 'نم' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب "نم" آهي. هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رس). شبنم، مائع، رس. افسانوي درياهه. جيڪو [[سنڌو درياھ|سنڌو درياهه]] جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ [[هيروڊوٽس]] وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|اسٽاروووزسڪي پل - [[ٽوير اوبلاسٽ|ٽوير اوبلاست]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|وولگا هائيڊرو اليڪٽرڪ اسٽيشن]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|[[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾ اوڪا (کاٻي پاسي) ۽ وولگا جو سنگم]] * اختابو (وولارزسڪي جي ويجهو)، هڪ تقسيم ڪندڙ * بالشوائي ارجيز (وولسڪ جي ويجهو) * سمارا ([[سمارا اوبلاسٽ|سامارا اوبلاست]] ۾) * ڪاما (ڪازان جي ڏکڻ) * قازانڪا (قازان ۾) * سوويگا (اولهه قازان) * ويٽلوگا (ڪوزموڊيميانسڪ جي ويجهو) * سورا (واسيلسرسڪ ۾) * کيرزينٽس (ليسڪووو جي ويجهو) * اوکا (نزني نوگوروڊ ۾) * ازولا (بلخنا جي ويجهو) * اونڌا (يورويٽس جي ويجهو) * ڪوسٽروما (ڪوسٽروما ۾) * ڪوٽوروسل (ياروسلاو ۾) * شيڪسينا (چيريپو ويٽس ۾) * مولوگا (ويسگنسک جي ويجهو) * ڪاشينڪا (ڪليزين جي ويجهو) * نيرل (ڪليزين جي ويجهو) * ميڊويدتسا (ڪيمروو جي ويجهو) * ڊبنا (ڊبنا ۾) * شوشا (ڪوناڪوو جي ويجهو) * ٽويرٽسا (ٽوير اوبلاست ۾) * وازوزا (زيوبٽسو ۾) * سيلزهارووڪا (سيلزهاروو ۾) ==== آبي ذخيرا (لاڙ کان مٿي تائين) ==== * سوويت دور ۾ وولگا تي ڪيترائي وڏا هائيڊرو اليڪٽرڪ ذخيرا تعمير ڪيا ويا. اهي آهن: * وولگوگراڊ ذخيرو * ساراٽوف ذخيرو * ڪوئبيشيف ذخيرو - مٿاڇري جي لحاظ کان يورپ ۾ سڀ کان وڏو * چيبوڪسري ذخيرو * گورڪي ذخيرو * ريبنسک ذخيرو * يوگليچ ذخيرو * ايوانڪوو ذخيرو ==== وولگا جي ڪنارن تي سڀ کان وڏا شهر ==== * قازان * نزني نووگوروڊ * سمارا * وولگوگراڊ * سراتوف * ٽولياٽِي * ياروسلاوِل * آسٽراخان * اوليانووسک * چيبوڪسري * ٽيور ==== وولگا جي پار پل ==== * ڪوسٽروما ريل پل === انساني تاريخ === [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] d7fhjxjwm4dc51nqe0uzoy1z9s2q1l2 371863 371862 2026-04-17T09:09:00Z Memon2025 21315 371863 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' ([[روسي ٻولي|روسي]]: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، [[روس]] ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ [[ڪيسپئن سمنڊ|ڪيسپين سمنڊ]] ۾ وهندو آهي. وولگا جي ڊيگهه <small>3,531</small> ڪلوميٽر (<small>2,194</small> ميل) آهي ۽ ان جو ڪيچمينٽ ايريا <small>13,60,000</small> چورس ڪلوميٽر (<small>5,30,000</small> چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، <small>8,000</small> ۽ <small>8,500</small> ڪيوبڪ ميٽر (<small>2,80,000</small> ۽ <small>3,00,000</small> ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي وڏي پيماني تي روس جي قومي درياهه طور سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، [[ماسڪو]] سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا [[ڪيسپئن سمنڊ|ڪئسپين سمنڊ]] ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاوڪ لفظ "vòlga" 'نم' مان نڪتل آهي. جيڪو ڪيترين ئي سلاوڪ ٻولين ۾ محفوظ آهي. وولگا (влага, نمي; بلغاريا; سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها "نمي) وولگا جو سٿين نالو "راها", لفظي معنيٰ 'نم' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب "نم" آهي. هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رس). شبنم، مائع، رس. افسانوي درياهه. جيڪو [[سنڌو درياھ|سنڌو درياهه]] جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ [[هيروڊوٽس]] وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|اسٽاروووزسڪي پل - [[ٽوير اوبلاسٽ|ٽوير اوبلاست]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|وولگا هائيڊرو اليڪٽرڪ اسٽيشن]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|[[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾ اوڪا (کاٻي پاسي) ۽ وولگا جو سنگم]] * اختابو (وولارزسڪي جي ويجهو)، هڪ تقسيم ڪندڙ * بالشوائي ارجيز (وولسڪ جي ويجهو) * سمارا ([[سمارا اوبلاسٽ|سامارا اوبلاست]] ۾) * ڪاما (ڪازان جي ڏکڻ) * قازانڪا (قازان ۾) * سوويگا (اولهه قازان) * ويٽلوگا (ڪوزموڊيميانسڪ جي ويجهو) * سورا (واسيلسرسڪ ۾) * کيرزينٽس (ليسڪووو جي ويجهو) * اوڪا ([[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾) * ازولا (بلخنا جي ويجهو) * اونڌا (يورويٽس جي ويجهو) * ڪوسٽروما ([[ڪوسٽروما اوبلاسٽ|ڪوسٽروما]] ۾) * ڪوٽوروسل ([[ياروسلاول اوبلاسٽ|ياروسلاو]] ۾) * شيڪسينا (چيريپو ويٽس ۾) * مولوگا (ويسگنسک جي ويجهو) * ڪاشينڪا (ڪليزين جي ويجهو) * نيرل (ڪليزين جي ويجهو) * ميڊويدتسا ([[ڪيمرووو اوبلاسٽ|ڪيمروو]] جي ويجهو) * ڊبنا (ڊبنا ۾) * شوشا (ڪوناڪوو جي ويجهو) * ٽويرٽسا ([[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾) * وازوزا (زيوبٽسو ۾) * سيلزهارووڪا (سيلزهاروو ۾) ==== آبي ذخيرا (لاڙ کان مٿي تائين) ==== * سوويت دور ۾ وولگا تي ڪيترائي وڏا هائيڊرو اليڪٽرڪ ذخيرا تعمير ڪيا ويا. اهي آهن: * وولگوگراڊ ذخيرو * ساراٽوف ذخيرو * ڪوئبيشيف ذخيرو - مٿاڇري جي لحاظ کان يورپ ۾ سڀ کان وڏو * چيبوڪسري ذخيرو * گورڪي ذخيرو * ريبنسک ذخيرو * يوگليچ ذخيرو * ايوانڪوو ذخيرو ==== وولگا جي ڪنارن تي سڀ کان وڏا شهر ==== * قازان * نزني نووگوروڊ * سمارا * وولگوگراڊ * سراتوف * ٽولياٽِي * ياروسلاوِل * آسٽراخان * اوليانووسک * چيبوڪسري * ٽيور ==== وولگا جي پار پل ==== * ڪوسٽروما ريل پل === انساني تاريخ === [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|Many [[Russian Orthodox Church|Orthodox]] [[shrine]]s and [[monasteries]] are located along the banks of the Volga]] The Volga–[[Oka (river)|Oka]] region has been occupied for at least 9,000 years and supported a bone and antler industry for producing bone arrowheads, spearheads, lanceheads, daggers, hunters knives, and awls. The makers also used local quartz and imported flints.<ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> During [[classical antiquity]], the Volga formed the boundary between the territories of the [[Cimmerians]] in the Caucasian Steppe and the [[Scythians]] in the Caspian Steppe.<ref name="OlbrychtCimmerians"/> After the Scythians migrated to the west and displaced the Cimmerians, the Volga became the boundary between the territories of the Scythians in the Pontic and Caspian Steppes and the [[Massagetae]] in the Caspian and Transcaspian steppes.<ref name="OlbrychtNomads"/> Between the 6th and the 8th centuries, the [[Alans]] settled in the [[Middle Volga Area|Middle Volga]] region and in the steppes of Russia's southern region in the [[Pontic–Caspian steppe]].<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> The area around the Volga was inhabited by the [[Slavic tribes]] of [[Vyatichs]] and [[Buzhans]], by [[Finno-Ugric peoples|Finno-Ugric]], [[North Germanic peoples|Scandinavian]], [[Balts|Baltic]], [[Huns|Hunnic]] and [[Turkic peoples]] ([[Tatar language|Tatars]], [[Kipchak languages|Kipchaks]], [[Khazar language|Khazars]]) in the [[first millennium]] AD, replacing the [[Scythians]].<ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref>{{Unreliable source?|date=October 2024|reason=Source is a Master's thesis}} Furthermore, the river played a vital role in the commerce of the [[Byzantine Empire|Byzantine people]]. The ancient scholar [[Ptolemy]] of [[Alexandria]] mentions the lower Volga in his ''Geography'' (Book 5, Chapter 8, 2nd Map of Asia). He calls it the ''Rha'', which was the Scythian name for the river. Ptolemy believed the Don and the Volga shared the same upper branch, which flowed from the [[Hyperborean]] Mountains. Between 2nd and 5th centuries [[Balts|Baltic people]] were very widespread in today's European Russia. Baltic people were widespread from [[Sozh River]] till today's Moscow and covered much of today's [[Central Russia]] and intermingled with the East Slavs.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> The Russian ethnicity in Western Russia and around the Volga river evolved to a very large extent, next to other tribes, out of the East Slavic tribe of the [[Buzhans]] and [[Vyatichi]]s. The Vyatichis were originally concentrated on the Oka River.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> Furthermore, several localities in Russia are connected to the Slavic Buzhan tribe, like for example [[Sredniy Buzhan]] in the [[Orenburg Oblast]], Buzan and the [[Buzan River]] in the [[Astrakhan Oblast]].<ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> Buzhan ({{langx|fa|بوژان{{lrm}}|Būzhān}}; also known as ''Būzān'') is also a village in [[Buzhan, Nishapur|Nishapur]], [[Iran]]. In late 8th century the Russian state Russkiy Kaganate is recorded in different Northern and Oriental sources. The Volga was one of the main rivers of the Rus' Khaganates culture.<ref name="Gannholm"/> Subsequently, the river basin played an important role in the movements of peoples from [[Asia]] to [[Europe]]. A powerful polity of [[Volga Bulgaria]] once flourished where the [[Kama (river)|Kama]] joins the Volga, while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] climfs7s1gvkmk9c9q56ptv9haxw628 371864 371863 2026-04-17T09:30:59Z Memon2025 21315 371864 wikitext text/x-wiki {{Short description|River in Russia; longest river in Europe}} {{Infobox river | name = وولگا<br>Volga | native_name = Волга | name_other = | name_etymology = "وولگا" (vòlga نم پروٽو سلوڪ) | image = Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg | image_size = 300 | image_caption = وولگا ياروسلاول ۾ | map = volgarivermap.png | map_size = 300 | map_caption = وولگا جي نيڪال جو حوض | pushpin_map = | pushpin_map_size = 300 | pushpin_map_caption = | subdivision_type1 = جڳھ | subdivision_name1 = [[اوڀر يورپ]] | subdivision_type2 = [[ملڪ]] | subdivision_name2 = [[روس|روسي فيڊريشن]] | subdivision_type3 = وفاقي مضمون | subdivision_name3 = [[ٽوير اوبلاسٽ]] • [[ماسڪو اوبلاسٽ]] • [[ياروسلاول اوبلاسٽ]] • [[ماري ايل|جمهوريه ماري ايل]] [[چوواشيا|جمهوريه چوواشيا]] • [[تاتارستان|جمهوريه تاتارستان]] • [[سمارا اوبلاسٽ]] • [[ساراتوف اوبلاسٽ]] • [[آستراخان اوبلاسٽ]] • [[ڪالميڪيا|جمهوريه ڪالميڪيا]] • [[ڪوسٽروما اوبلاسٽ]] • [[نزني نووگوروڊ اوبلاسٽ]] • [[اليانووسڪ اوبلاسٽ|اُليانووسڪ اوبلاسٽ]] • [[آئيوانووو اوبلاسٽ]] • [[وولگوگراڊ اوبلاست|وولگوگراڊ اوبلاسٽ]] | subdivision_type4 = [[شهر]] | subdivision_name4 = ٽوير • ياروسلاول • نزني نووگوروڊ • چيبوڪسري • قازان • اُوليانووسڪ • سمارا • ساراتوف • وولگوگراڊ • آسترخان • ٽوگليٽي | length = 3531 ڪلوميٽر<ref name=gvr/> | width_min = | width_avg = | width_max = | depth_min = | depth_avg = | depth_max = | discharge1_location = آستراخان (بيسن جي ماپ: 13,91,271 چورس ڪلوميٽر) | discharge1_min = 5000 ڪيوبڪ ميٽر في سيڪن | discharge1_avg = 8060 ڪيوبڪ ميٽر في سيڪنڊ 8103 ڪيوبڪ ميٽر في سيڪنڊ [[وولگا ڊيلٽا]] 111 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto"/> | discharge1_max = 48500 ڪيوبڪ ميٽر في سيڪن | source1 = | source1_location = والڊائي ٽڪريون , [[ٽوير اوبلاسٽ]] | source1_coordinates = {{coord|57|15|4.7|N|32|28|5.1|E|display=inline}} | source1_elevation = 228 ميٽر<ref name="readersnatural" /> | mouth = [[ڪيسپيئن سمنڊ]] | mouth_location = [[آستراخان اوبلاسٽ]] | mouth_coordinates = {{coord|45|41|42|N|47|53|51|E|display=inline,title}}<ref>{{GEOnet2|32FA87888EC23774E0440003BA962ED3|Volga}}</ref> | mouth_elevation = 28 ميٽر<ref name="readersnatural" /> | progression = | river_system = | basin_size = 13,60,000 چورس ڪلوميٽر <ref name=gvr/> 14,04,108 چورس ڪلوميٽر<ref name="auto"/> | tributaries_left = ڪاما ندي | tributaries_right = اوڪا ندي | custom_label = | custom_data = | discharge2_location = وولگوگراڊ (بيسن جي ماپ: 13,59,397 چورس ڪلوميٽر) | discharge2_min = 5090 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_avg = 8150 ڪيوبڪ ميٽر في سيڪنڊ | discharge2_max = 48,450 ڪيوبڪ ميٽر في سيڪنڊ | discharge3_location = سمارا (بيسن جي ماپ: 12,18,995 چورس ڪلوميٽر) | discharge3_avg = 7,680 ڪيوبڪ ميٽر في سيڪنڊ | discharge4_location = نزني نووگوروڊ (بيسن جي ماپ: 4,97,637 چورس ڪلوميٽر) | discharge4_avg = 2,940 ڪيوبڪ ميٽر في سيڪنڊ<br> 2,806 ڪيوبڪ ميٽر في سيڪنڊ ياروسلاول (بيسن جي ماپ: 153658 چورس ڪلوميٽر): 1,008 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> رائبنسک (بيسن جي ماپ: 125120 چورس ڪلوميٽر): 993 ڪيوبڪ ميٽر في سيڪنڊ <ref name="auto2"/> | discharge5_location = ٽوير (بيسن جي ماپ: 24,659 چورس ڪلوميٽر) | discharge5_avg = 176 ڪيوبڪ ميٽر في سيڪنڊ<br> 186 ڪيوبڪ ميٽر في سيڪنڊ<ref name="auto2"/> | mapframe = yes | mapframe-frame-width = 300 | mapframe-wikidata=yes | mapframe-zoom=4 | mapframe-height=250 | mapframe-stroke-width=3 }} [[File:Yaroslavl. Volga River. Cathedral of the Dormition P5212700 2200.jpg|thumb|اوليانوفسڪ جي ويجهو وولگا ندي]] '''وولگا''' ([[روسي ٻولي|روسي]]: Волга) يورپ جو سڀ کان ڊگهو درياهه ۽ دنيا جو سڀ کان ڊگهو اينڊورهائيڪ بيسن درياهه، [[روس]] ۾ واقع آهي.<ref>{{cite web|url=https://www.worldatlas.com/rivers/10-longest-rivers-in-europe.html|title=10 Longest Rivers In Europe}}</ref> اهو وچ روس مان ڏکڻ روس ۽ [[ڪيسپئن سمنڊ|ڪيسپين سمنڊ]] ۾ وهندو آهي. وولگا جي ڊيگهه <small>3,531</small> ڪلوميٽر (<small>2,194</small> ميل) آهي ۽ ان جو ڪيچمينٽ ايريا <small>13,60,000</small> چورس ڪلوميٽر (<small>5,30,000</small> چورس ميل) آهي. اهو ڊيلٽا تي سراسري خارج ٿيڻ، <small>8,000</small> ۽ <small>8,500</small> ڪيوبڪ ميٽر (<small>2,80,000</small> ۽ <small>3,00,000</small> ڪيوبڪ فوٽ) في سيڪنڊ جي وچ ۾، جي لحاظ کان يورپ جو سڀ کان وڏو درياهه پڻ آهي<ref name="gvr2">[http://textual.ru/gvr/index.php?card=179058 «Река Волга»] {{Webarchive|url=https://web.archive.org/web/20160305021422/http://textual.ru/gvr/index.php?card=179058|date=5 March 2016}}, Russian State Water Registry</ref> ۽ نيڪال جي بيسن جي لحاظ کان ان کي وڏي پيماني تي روس جي قومي درياهه طور سمجهيو ويندو آهي. پراڻي روسي رياست، روس خگنيٽ، تقريبن 830 عيسوي ۾ وولگا جي ڪناري تي پيدا ٿي. <ref name="Gannholm2">{{Cite web|last=Gannholm|first=Tore|title=Birka, Varangian Emporium|url=https://www.academia.edu/40313672|language=en|access-date=15 August 2020|archive-date=18 April 2022|archive-url=https://web.archive.org/web/20220418181057/https://www.academia.edu/40313672|url-status=live}}</ref> تاريخي طور تي درياهه مختلف يوريشيائي تهذيبن جي هڪ اهم ملاقات جي جڳهه طور ڪم ڪيو.<ref>{{Cite book |title=Grand Strategy of the Byzantine Empire |last=Luttwak, Edward N. |date=2011 |publisher=Belknap Harvard |isbn=978-0674062078 |pages=52 |oclc=733913679}}</ref><ref>{{Cite journal |last=Walker |first=Joel |date=2007 |title=Iran and Its Neighbors in Late Antiquity: Art of the Sasanian Empire (224–642 C.E.) |journal=American Journal of Archaeology |volume=1 11 |issue=4 |pages=797 |doi=10.3764/aja.111.4.795 |s2cid=192943660 |issn=0002-9114}}</ref><ref>{{Cite book |title=The Volga river |last=McNeese |first=Tim |date=2005 |publisher=Chelsea House Publishers |isbn=0791082474 |location=Philadelphia |pages=14–16 |oclc=56535045}}</ref> درياهه روس ۾ ٻيلن ۽ ميدانن مان وهندو آهي. قوم جي گاديءَ جي هنڌ، [[ماسڪو]] سميت، روس جي ڏهن وڏن شهرن مان پنج، وولگا جي نيڪال واري بيسن ۾ واقع آهن. ڇاڪاڻ ته وولگا [[ڪيسپئن سمنڊ|ڪئسپين سمنڊ]] ۾ وهندو آهي، جيڪو هڪ اندروني پاڻي جو جسم آهي، وولگا قدرتي طور تي دنيا جي ڪنهن به سمنڊ سان ڳنڍيل ناهي. دنيا جا ڪجهه وڏا پاڻي جا ذخيرا وولگا ندي جي ڪناري تي واقع آهن. روسي ثقافت ۾ درياهه جو هڪ علامتي مطلب آهي. روسي ادب ۽ لوڪ ڪهاڻيون اڪثر ڪري ان کي "وولگا-ماتوشڪا" (روسي: Волга-матушка، مادر وولگا) جي نالي سان سڏين ٿا. ==نالو== روسي نالو وولگا (Волга) پروٽو-سلاوڪ لفظ "vòlga" 'نم' مان نڪتل آهي. جيڪو ڪيترين ئي سلاوڪ ٻولين ۾ محفوظ آهي. وولگا (влага, نمي; بلغاريا; سربو-ڪروشين: سلووين. پولش. مقدونيائي ۽ چيڪ: ولها "نمي) وولگا جو سٿين نالو "راها", لفظي معنيٰ 'نم' هو. هي هڪ افسانوي وهڪري جي اويستا نالي سان لاڳاپيل آهي، راها (𐬭𐬀𐬢𐬵𐬁)، جنهن جو مطلب "نم" آهي. هن نالي جو مقابلو ڪيترن ئي هند-ايراني اصطلاحن سان ڪري سگهجي ٿو، جهڙوڪ: سوگديان رڪ (𐽀𐼰𐼸‎) 'رڳ، رت جي رڳ' (پراڻي ايراني: راهاڪا مان). فارسي: رڳ. رڳ. ويدڪ سنسڪرت: راسا (رس). شبنم، مائع، رس. افسانوي درياهه. جيڪو [[سنڌو درياھ|سنڌو درياهه]] جي هڪ معاون ندي جو نالو پڻ هو. سٿين نالو جديد موڪشا ۾ را (Рав) جي نالي سان زنده آهي. يوناني ليکڪ [[هيروڊوٽس]] وولگا جا ٻه وڌيڪ قديم ايراني نالا درج ڪيا آهن: * اوارو (قديم يوناني: Ὄαρος, اورس). جيڪو سٿين مان نڪتل آهي: وارو، جنهن جي معنيٰ آهي "وسيع". ڊنيپر نديءَ جو هون نالو، وار، پڻ سٿين مان نڪتل آهي: وارو. * اراڪسس (قديم يوناني: Ἀράξης, ارڪسس). درياهه جي ڪناري تي رهندڙ ترڪ ماڻهو اڳ ۾ ان کي اتيل يا اتيل سڏيندا هئا. جديد ترڪ ٻولين ۾. وولگا کي تاتار ۾ İdel (Идел) جي نالي سان سڃاتو وڃي ٿو. چواش ۾ اتال (Атӑл). بشڪير ۾ ايزل. قازق ۾ ايڊيل، ۽ ترڪي ۾ اِدل. ترڪ نالا قديم ترڪ روپ "ايتل/ايرتل" ڏانهن واپس وڃن ٿا، جنهن جي اصليت ۽ معنيٰ واضح ناهي. شايد هن شڪل جو هائيڊرونيم ارتيش سان تعلق آهي. * ترڪ ماڻهن اِتل جي اصليت کي ڪاما سان ڳنڍيو. اهڙيءَ طرح، ڪاما جي هڪ کاٻي شاخ کي آق اِتل 'اڇو اِتل' جو نالو ڏنو ويو جيڪو جديد شهر اوفا ۾ ڪارا اِتل 'ڪارو اِتل' سان ملائي ٿو. انڊيل (انڊيل) جو نالو چرڪس ٻولي ۾ استعمال ٿيندو آهي. * ايشيا ۾ درياهه کي ان جي ٻئي ترڪ نالو سارِ-سو 'پيلو پاڻي' سان سڃاتو ويندو هو، پر اوئرات پڻ پنهنجو نالو، اِجل مورون يا 'موافقت درياءَ' استعمال ڪندا هئا. هن وقت ماري، هڪ ٻيو يورالڪ گروهه، درياهه کي جُل (Юл) سڏيندو آهي، جنهن جي معنيٰ تاتار ۾ 'رستو' آهي. ==وضاحت== [[File:Саратовский мост.jpeg|alt=|thumb|رات جو ساراتوف پل، [[ساراتوف اوبلاسٽ|ساراتوف اوبلاست]]]] [[File:Staritsa.jpg|thumb|اسٽارٽسا جي ويجهو مٿئين وولگا، 1912]] [[File:ISS-60 Volga River flowing into the Caspian Sea.jpg|alt=Large river ending in triangular delta into sea, seen from above the atmosphere|thumb|بين الاقوامي خلائي اسٽيشن تان وولگا ڊيلٽا جو نظارو]] وولگا [[يُورَپ|يورپ]] جو سڀ کان ڊگهو درياهه آهي ۽ ان جو ڪيچمينٽ جو علائقو تقريبن مڪمل طور تي روس جي اندر آهي. جيتوڻيڪ روس ۾ سڀ کان ڊگهو درياهه اوب-ارٽيش ندي نظام آهي. اهو ڪيسپين سمنڊ جي بند بيسن سان تعلق رکي ٿو. بند بيسن ۾ وهندڙ سڀ کان ڊگهو درياهه آهي. وولگا جو ذريعو [[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾ وولگوورخووي ڳوٺ ۾ آهي. [[ماسڪو]] جي اتر اولهه ۾ سمنڊ جي سطح کان 225 ميٽر (738 فوٽ) مٿي ۽ [[سينٽ پيٽرسبرگ]] کان تقريباً <small>320</small> ڪلوميٽر (<small>200</small> ميل) ڏکڻ اوڀر ۾ والڊائي ٽڪرين ۾ اڀري ٿو. وولگا اوڀر طرف ڍنڍ اسٽرز، ٽور، ڊبنا، رائبنسک، ياروسلاول، نزني نوگوروڊ ۽ قازان کان گذري ٿو. اتان کان اهو ڏکڻ طرف موڙ ڪري ٿو ۽ يوليانووسڪ، ٽولياٽِي، سمارا، سراتوف ۽ وولگوگراڊ مان وهندو آهي ۽ سمنڊ جي سطح کان 28 ميٽر (92 فوٽ) هيٺ آسٽرخان کان هيٺ ڪيسپين سمنڊ ۾ ڇوڙ ڪري ٿو. وولگا ۾ ڪيتريون ئي معاون نديون آهن. سڀ کان اهم ڪاما، اوڪا، ويٽلوگا ۽ سورا. وولگا ۽ ان جون شاخون وولگا نديءَ جو نظام ٺاهين ٿيون, جيڪو لڳ ڀڳ <small>13,50,000</small> چورس ڪلوميٽر (<small>5,20,000</small> چورس ميل) جي ايراضيءَ مان وهي ٿو. اهو روس جي سڀ کان وڌيڪ آبادي واري حصي ۾ وهندو آهي. وولگا ڊيلٽا جي ڊيگهه لڳ ڀڳ 160 ڪلوميٽر (99 ميل) آهي ۽ ان ۾ 500 چينل ۽ ننڍا نديون شامل آهن. يورپ ۾ سڀ کان وڏو درياهه, اهو روس ۾ واحد جڳهه آهي جتي پيليڪن، فليمنگو ۽ لوٽس ملي سگهن ٿا. وولگا هر سال ٽن مهينن تائين پنهنجي ڊيگهه جو گهڻو حصو منجمد رهي ٿو. وولگا اولهاهين روس جي گهڻي حصي کي پاڻي ڏئي ٿو. ان جا ڪيترائي وڏا ذخيرا آبپاشي ۽ هائيڊرو اليڪٽرڪ پاور فراهم ڪن ٿا. ماسڪو ڪينال، وولگا-ڊان ڪينال ۽ وولگا-بالٽڪ واٽر وي ماسڪو کي اڇي سمنڊ، بالٽڪ سمنڊ، ڪيسپين سمنڊ، ازوف سمنڊ ۽ ڪاري سمنڊ سان ڳنڍيندڙ نيويگيبل واٽر وي ٺاهين ٿا. ڪيميائي آلودگي جي اعليٰ سطح درياءَ ۽ ان جي رهائش کي خراب طور تي متاثر ڪيو آهي.<ref name="readersnatural">{{Cite book |title=Natural Wonders of the World |publisher=Reader's Digest Association, Inc |year=1980 |isbn=0-89577-087-3 |editor-last=Scheffel |editor-first=Richard L. |location=United States of America |pages=406 |editor-last2=Wernet |editor-first2=Susan J.}}</ref> زرخيز درياءَ جي وادي ڪڻڪ ۽ ٻيون زرعي پيداوار ۽ ان ۾ ڪيتريون ئي معدني دولت پڻ آهي. وولگا وادي تي هڪ اهم پيٽروليم صنعت جو مرڪز آهي. ٻين وسيلن ۾ قدرتي گئس، لوڻ ۽ پوٽاش شامل آهن. وولگا ڊيلٽا ۽ ڪيسپين سمنڊ مڇي مارڻ جا ميدان آهن. === سنگم (هيٺئين وهڪري کان مٿي واري وهڪري تائين) === [[File:Tver dusk 3.jpg|thumb|اسٽاروووزسڪي پل - [[ٽوير اوبلاسٽ|ٽوير اوبلاست]]|alt=]] [[File:Volga Hydroelectric Station 002 (cropped).JPG|thumb|وولگا هائيڊرو اليڪٽرڪ اسٽيشن]] [[File:Nizhny Novgorod P8132254 2200.jpg|thumb|[[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾ اوڪا (کاٻي پاسي) ۽ وولگا جو سنگم]] * اختابو (وولارزسڪي جي ويجهو)، هڪ تقسيم ڪندڙ * بالشوائي ارجيز (وولسڪ جي ويجهو) * سمارا ([[سمارا اوبلاسٽ|سامارا اوبلاست]] ۾) * ڪاما (ڪازان جي ڏکڻ) * قازانڪا (قازان ۾) * سوويگا (اولهه قازان) * ويٽلوگا (ڪوزموڊيميانسڪ جي ويجهو) * سورا (واسيلسرسڪ ۾) * کيرزينٽس (ليسڪووو جي ويجهو) * اوڪا ([[نزني نووگوروڊ اوبلاسٽ|نزني نوگوروڊ]] ۾) * ازولا (بلخنا جي ويجهو) * اونڌا (يورويٽس جي ويجهو) * ڪوسٽروما ([[ڪوسٽروما اوبلاسٽ|ڪوسٽروما]] ۾) * ڪوٽوروسل ([[ياروسلاول اوبلاسٽ|ياروسلاو]] ۾) * شيڪسينا (چيريپو ويٽس ۾) * مولوگا (ويسگنسک جي ويجهو) * ڪاشينڪا (ڪليزين جي ويجهو) * نيرل (ڪليزين جي ويجهو) * ميڊويدتسا ([[ڪيمرووو اوبلاسٽ|ڪيمروو]] جي ويجهو) * ڊبنا (ڊبنا ۾) * شوشا (ڪوناڪوو جي ويجهو) * ٽويرٽسا ([[ٽوير اوبلاسٽ|ٽوير اوبلاست]] ۾) * وازوزا (زيوبٽسو ۾) * سيلزهارووڪا (سيلزهاروو ۾) ==== آبي ذخيرا (لاڙ کان مٿي تائين) ==== * سوويت دور ۾ وولگا تي ڪيترائي وڏا هائيڊرو اليڪٽرڪ ذخيرا تعمير ڪيا ويا. اهي آهن: * وولگوگراڊ ذخيرو * ساراٽوف ذخيرو * ڪوئبيشيف ذخيرو - مٿاڇري جي لحاظ کان يورپ ۾ سڀ کان وڏو * چيبوڪسري ذخيرو * گورڪي ذخيرو * ريبنسک ذخيرو * يوگليچ ذخيرو * ايوانڪوو ذخيرو ==== وولگا جي ڪنارن تي سڀ کان وڏا شهر ==== * قازان * نزني نووگوروڊ * سمارا * وولگوگراڊ * سراتوف * ٽولياٽِي * ياروسلاوِل * آسٽراخان * اوليانووسک * چيبوڪسري * ٽيور ==== وولگا جي پار پل ==== * ڪوسٽروما ريل پل === انساني تاريخ === [[File:Volga River. Tolga Monastery P5212881 2200.jpg|thumb|ڪيتريون ئي آرٿوڊوڪس مزارون ۽ خانقاهون وولگا نديءَ جي ڪناري تي واقع آهن.]] وولگا-اوڪا علائقو گهٽ ۾ گهٽ 9,000 سالن کان قبضو ڪري رهيو آهي ۽ هڏن ۽ سينگار جي صنعت کي سهارو ڏنو ته جيئن هڏن جا تير، نيزا، خنجر ۽ شڪاري چاقو پيدا ٿين. ٺاهيندڙن مقامي ڪوارٽز ۽ درآمد ٿيل چقمق پڻ استعمال ڪيا. <ref>Zhilin, M. (2015). Early Mesolithic bone arrowheads from the Volga-Oka interfluve, central Russia. 32. 35-54.</ref> ڪلاسيڪل قديم دور ۾ وولگا ڪاڪيشين اسٽيپ ۾ سميرينز ۽ ڪيسپين اسٽيپ ۾ سٿينز جي علائقن جي وچ ۾ حد ٺاهي. سٿينز جي اولهه ڏانهن لڏپلاڻ ۽ سميرينز کي بي دخل ڪرڻ کان پوءِ، وولگا پونٽڪ ۽ ڪيسپين اسٽيپس ۾ سٿينز ۽ ڪيسپين ۽ ٽرانسڪيپين اسٽيپس ۾ مسجيٽا جي علائقن جي وچ ۾ حد بڻجي وئي. ڇهين ۽ اٺين صدي جي وچ ۾، الانس وچين وولگا علائقي ۾ ۽ روس جي ڏاکڻي علائقي جي پونٽڪ-ڪيپين اسٽيپس ۾ آباد ٿيا.<ref>{{Cite web |url=https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |title=VORGESCHICHE DER URALISCHEN SPRACHFAMILIE, GESCHICHTE DER KLEINEREN URALISCHEN SPRACHEN: CHRONOLOGIE |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190530052002/https://www.slm.uni-hamburg.de/ifuu/download/helimski/ural-vorgeschichte.pdf |archive-date=30 May 2019 |url-status=live}}</ref> وولگا جي چوڌاري وارو علائقو پهرين صدي عيسوي ۾ سلاو قبيلن وائيٽچ ۽ بوزان، فنو-يوگرڪ، اسڪينڊينيوين، بالٽڪ، هن ۽ ترڪ ماڻهن (تاتار، ڪپچڪ، خزار) پاران آباد ڪيو ويو هو، جنهن سٿين جي جاءِ ورتي. <ref>{{Cite thesis |url=http://www.etd.ceu.edu/2018/katona_csete.pdf |title=Co-operation between the Viking Rus' and the Turkic nomads of the steppe in the ninth-eleventh centuries |last=Katona |first=Cseste |type=MA thesis |publisher=Central European University |date=2018 |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20190418221818/http://www.etd.ceu.edu/2018/katona_csete.pdf |archive-date=18 April 2019 |url-status=live}}</ref> ان کان علاوه، درياهه بازنطيني ماڻهن جي واپار ۾ اهم ڪردار ادا ڪيو. قديم عالم ٽالمي آف اليگزينڊرريا پنهنجي جاگرافي (ڪتاب 5، باب 8، ايشيا جو ٻيو نقشو) ۾ هيٺين وولگا جو ذڪر ڪري ٿو. هو ان کي "را" سڏي ٿو، جيڪو درياءَ جو سٿين نالو هو. ٽالمي جو خيال هو ته ڊان ۽ وولگا ساڳي مٿئين شاخ شيئر ڪندا هئا، جيڪا هائپربورين جبلن مان وهندي هئي. ٻي ۽ پنجين صدي جي وچ ۾ بالٽڪ ماڻهو اڄ جي يورپي روس ۾ تمام گهڻا پکڙيل هئا. بالٽڪ ماڻهو سوز ندي کان اڄ جي ماسڪو تائين پکڙيل هئا ۽ اڄ جي مرڪزي روس جو گهڻو حصو ڍڪيندا هئا ۽ اوڀر سلاو سان ملائي ويندا هئا.<ref>{{Cite web |url=http://www.lituanus.org/1964/64_2_08_BR1.html |title=Marija Gimbutas. "A Survey Study of the Ancient Balts - Reviewed by Jonas Puzinas |website=www.lituanus.org |access-date=30 May 2019 |archive-url=https://web.archive.org/web/20190804192233/http://www.lituanus.org/1964/64_2_08_BR1.html |archive-date=4 August 2019 |url-status=live}}</ref> مغربي روس ۽ وولگا نديءَ جي چوڌاري روسي نسل, ٻين قبيلن سان گڏ، بوزان ۽ وِتياچي جي اوڀر سلاويڪ قبيلي مان تمام گهڻي حد تائين ترقي ڪئي. وِتياچي اصل ۾ اوڪا نديءَ تي مرڪوز هئا.<ref>{{Cite book |title=The Khazars: a Judeo-Turkish Empire on the Steppes, 7th-11th Centuries AD. |last=Zhirohov, Mikhail. |date=2019 |publisher=Bloomsbury Publishing Plc |others=Nicolle, David., Hook, Christa. |isbn=9781472830104 |location=London |pages=47 |oclc=1076253515}}</ref> ان کان علاوه، روس ۾ ڪيترائي علائقا سلاوڪ بوزان قبيلي سان ڳنڍيل آهن، مثال طور اورينبرگ اوبلاست ۾ سريڊني بوزان، آسترخان اوبلاست ۾ بوزان ندي. <ref>{{Cite web |url=http://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |title=Early East Slavic Tribes in Russia |website=Study.com |language=en |access-date=16 December 2018 |archive-url=https://web.archive.org/web/20190328092408/https://study.com/academy/lesson/early-east-slavic-tribes-in-russia.html |archive-date=28 March 2019 |url-status=live}}</ref> بوزان ايران جي نيشاپور ۾ هڪ ڳوٺ پڻ آهي. اٺين صدي جي آخر ۾ روسي رياست رسڪي ڪاگنيٽ مختلف اتر ۽ مشرقي ذريعن ۾ درج ٿيل آهي. وولگا روس جي خگانيٽ ثقافت جي مکيه دريائن مان هڪ هئي. بعد ۾، درياءَ جي بيسن ايشيا کان يورپ تائين ماڻهن جي حرڪت ۾ اهم ڪردار ادا ڪيو. وولگا بلغاريا جي هڪ طاقتور سياست هڪ ڀيرو اتي ترقي ڪئي جتي ڪاما وولگا ۾ شامل ٿئي ٿي. And. while [[Khazaria]] controlled the lower stretches of the river. Such Volga cities as [[Atil]], [[Saqsin]], or [[Sarai (city)|Sarai]] were among the largest in the medieval world. The river [[Volga trade route|served as an important trade route]] connecting [[Viking Age|Scandinavia]], [[Baltic Finnic peoples|Finnic]] areas with the various Slavic tribes and Turkic, [[Germanic peoples|Germanic]], Finnic and other people in Old [[Rus' (people)|Rus']], and [[Volga Bulgaria]] with [[Khazars|Khazaria]], [[Persia]] and the [[Arab world]]. [[File:Ilia Efimovich Repin (1844-1930) - Volga Boatmen (1870-1873).jpg|thumb|upright=1.15|right|[[Ilya Yefimovich Repin]]'s 1870–1873 painting ''[[Barge Haulers on the Volga]]'']] Khazars were replaced by [[Kipchaks]], [[Kimeks]] and [[Mongols]], who founded the [[Golden Horde]] in the lower reaches of the Volga. Later their empire divided into the [[Khanate of Kazan]] and [[Khanate of Astrakhan]], both of which were conquered by the Russians in the course of the 16th century [[Russo-Kazan Wars]]. The Russian people's deep feeling for the Volga echoes in national culture and literature, starting from the 12th century [[Lay of Igor's Campaign]].<ref>{{cite web |url=http://www.volgawriter.com/VW%20Volga%20River.htm |title=The Volga |publisher=www.volgawriter.com |access-date=11 June 2010 |format=[[Microsoft FrontPage]] 12.0 |archive-url=https://web.archive.org/web/20100620141913/http://www.volgawriter.com/VW%20Volga%20River.htm |archive-date=20 June 2010 |url-status=dead}}</ref> [[The Volga Boatman's Song]] is one of many songs devoted to the national river of Russia. Construction of [[Soviet Union]]-era dams often involved enforced resettlement of huge numbers of people, as well as destruction of their historical heritage. For instance, the town of [[Mologa]] was flooded for the purpose of constructing the [[Rybinsk Reservoir]] (then the largest artificial lake in the world). The construction of the [[Uglich Reservoir]] caused the flooding of several monasteries with buildings dating from the 15th and 16th centuries. In such cases the ecological and cultural damage often outbalanced any economic advantage.<ref>"In all, Soviet dams flooded 2,600 villages and 165 cities, almost 78,000&nbsp;sq. km. – the area of Maryland, Delaware, Massachusetts, and New Jersey combined – including nearly 31,000&nbsp;sq. km. of agricultural land and 31,000&nbsp;sq. km. of forestland". Quoted from: Paul R. Josephson. ''Industrialized Nature: Brute Force Technology and the Transformation of the Natural World''. Island Press, 2002. {{ISBN|1-55963-777-3}}. Page 31.</ref> ====20th-century conflicts==== {{Main|Battle of Stalingrad|Kazan Operation}} [[File:Soviet marines-in the battle of stalingrad volga banks.jpg|thumb|right|upright=0.9|[[Soviet Union|Soviet]] [[Russian Naval Infantry#World War II|Marines]] charge the Volga [[Bank (geography)|river bank]].]] During the [[Russian Civil War]], both sides fielded warships on the Volga. In 1918, the Red [[Volga Flotilla]] participated in driving the Whites eastward, from the Middle Volga [[Kazan Operation|at Kazan]] to the Kama and eventually to [[Ufa]] on the [[Belaya River (Kama)|Belaya]].<ref>[[Brian Pearce]], [https://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm Introduction] ({{Webarchive |url=https://web.archive.org/web/20080203140800/http://www.marxists.org/history/ussr/government/red-army/1918/raskolnikov/ilyin/index.htm |date=3 February 2008 }}) to [[Fyodor Raskolnikov]]'s ''Tales of Sub-lieutenant Ilyin''.</ref> During the Civil War, [[Joseph Stalin]] ordered the imprisonment of several military specialists on a barge in the Volga and the sinking of a floating prison in which the officers perished.<ref>{{cite book |last1=Brackman |first1=Roman |title=The Secret File of Joseph Stalin: A Hidden Life |date=23 November 2004 |publisher=Routledge |isbn=978-1-135-75840-0 |page=129 |url=https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |language=en |access-date=30 October 2023 |archive-date=3 October 2023 |archive-url=https://web.archive.org/web/20231003000731/https://books.google.com/books?id=PY2RAgAAQBAJ&dq=stalin+trotsky+military+specialist&pg=PA129 |url-status=live }}</ref><ref>{{cite book |last1=Sebag Montefiore |first1=Simon |title=Stalin : the court of the red tsar |date=2004 |publisher=Grown House |location=London |isbn=978-0-7538-1766-7 |page=34 |url=https://archive.org/details/stalincourtofred0000seba/page/34/mode/1up?q=Enmity}}</ref> During World War II, the city on the big bend of the Volga, currently known as [[Volgograd]], witnessed the [[Battle of Stalingrad]], possibly the [[List of battles by casualties|bloodiest battle]] in human history, in which the Soviet Union and the German forces were deadlocked in a [[stalemate]] battle for access to the river. The Volga was (and still is) a vital transport route between central Russia and the Caspian Sea, which provides access to the oil fields of the [[Apsheron Peninsula|Absheron Peninsula]]. [[Hitler]] planned to use access to the oil fields of [[Azerbaijan]] to fuel future German conquests. Apart from that, whoever held both sides of the river could move forces across the river, to defeat the enemy's [[fortification]]s beyond the river.<ref>{{cite web |url=http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |title=::The Battle of Stalingrad |publisher=Historylearningsite.co.uk |access-date=11 June 2010 |archive-url=https://web.archive.org/web/20150530123434/http://www.historylearningsite.co.uk/battle_of_stalingrad.htm |archive-date=30 May 2015 |url-status=live}}</ref> By taking the river, Hitler's [[Nazi Germany|Germany]] would have been able to move [[cargo|supplies]], [[gun]]s, and men into the northern part of Russia. At the same time, Germany could permanently deny this transport route by the Soviet Union, hampering its access to oil and to supplies via the [[Persian Corridor]]. For this reason, many [[Amphibious warfare|amphibious]] military assaults were brought about in an attempt to remove the other side from the banks of the river. In these battles, the Soviet Union was the main [[Offensive (military)|offensive]] side, while the [[Wehrmacht|German troops]] used a more [[defense (military)|defensive]] stance, though much of the fighting was [[close combat|close quarters combat]], with no clear offensive or defensive side. ==نسلي گروهه== ==نيويگيشن== ==سيٽلائيٽ تصويرون== ==ثقافتي اهميت== وولگا درياءَ جي ڪل ڊيگهه 3,531 ڪلوميٽر آهي. هي درياءُ پنهنجي وهڪري جي حوالي سان به يورپ جو سڀ کان وڏو درياءُ آهي. هن کي روس جو '''قومي درياءُ''' تسليم ڪيو ويندو آهي. تاريخي طور تي، هي درياءُ يوريشيا جي مختلف تهذيبن جي ميلاپ جو مرڪز رهيو آهي. روس جي قديم رياست "روس خگنيٽ" (Rus' Khaganate) لڳ ڀڳ 830ع ۾ هن درياءَ جي ڪناري تي وجود ۾ آئي هئي. == جاگرافيائي بناوٽ == وولگا درياءُ روس جي ٻيلن ۽ ميداني علائقن (steppes) مان گذري ٿو. روس جي ڏهن وڏن شهرن مان پنج شهر، بشمول گاديءَ جو هنڌ '''ماسڪو'''، هن درياءَ جي طاس (drainage basin) ۾ واقع آهن. ڇاڪاڻ ته وولگا ڪئسپين سمنڊ ۾ ڇوڙ ڪري ٿو، جيڪو چئني پاسن کان زمين سان گهيريل آهي، ان ڪري هي درياءُ قدرتي طور تي دنيا جي وڏن سمنڊن (Oceans) سان ڳنڍيل ناهي. == ثقافتي مقام == روسي ڪلچر ۾ وولگا کي هڪ علامتي حيثيت حاصل آهي. روسي ادب ۽ لوڪ ڪهاڻين ۾ هن کي اڪثر "وولگا ماتوشڪا" (Volga-Matushka) يعني '''"ماءُ وولگا"''' جي نالي سان ياد ڪيو ويندو آهي. دنيا جا ڪجهه وڏا بند (Reservoirs) پڻ هن درياءَ تي تعمير ٿيل آهن. {{Infobox River | name = وولگا ندي وولگا درياءُ (Volga) | image = Volga_River_near_Ulyanovsk.jpg | caption = روس ۾ وولگا درياءَ جو هڪ نظارو | source1_location = | mouth_location = | length = | basin_size = | discharge1_avg = | countries = |native_name=Bo|settlement_type=دريا ندي|image_size=250px|image_skyline=Volga_River_near_Ulyanovsk.jpg|imagesize=250px|image_caption=اوليانوفسڪ جي ويجهو وولگا ندي|native_name_lang=روسي ٻولي|type=وولگا ندي|subdivision_name={{flag|Russia}} [[روس]]|subdivision_name1=Moscow|subdivision_name2=والڊائي ٽڪريون|subdivision_name3=[[ڪيسپين سمنڊ]] ئ|subdivision_type=[[ملڪ]]|subdivision_type1=Cities|subdivision_type2=ماخذ جو هنڌ|subdivision_type3=وات جو هنڌ|subdivision_type4=ڊيگهه|subdivision_name4=3,531 ڪلوميٽر|subdivision_type5=بيسن جو سائز|subdivision_name5=1,360,000 چورس ڪلوميٽر|subdivision_type6=خارج ٿيڻ جو اوسط|subdivision_name6=8,060 ڪيوبڪ ميٽر في سيڪنڊ}} '''وولگا''' (روس) [[يورپ]] جو سڀ کان ڊگهو درياءُ آهي ۽ دنيا جو سڀ کان وڏو "اينڊورهيڪ" (endorheic) يعني اهڙو درياءُ آهي جيڪو ڪنهن کليل سمنڊ ۾ ڪرڻ بجاءِ هڪ بند سمنڊ (ڪئسپين سمنڊ) ۾ ڇوڙ ڪري ٿو. هي درياءُ [[روس]] ۾ واقع آهي ۽ وچ روس کان ڏکڻ روس تائين وهندو [[ڪيسپئن سمنڊ]] ۾ وڃي ڪري ٿو. ==وڌيڪ ڏسو== * [[ڪيسپئن سمنڊ|ڪئسپيئن سمنڊ]] ==حوالا== {{حوالا}} ==ٻاهرين لنڪس== {{Commons category|وولگا}} * {{Cite EB1911|wstitle= Volga |volume= 28 |last1= Kropotkin |first1= Peter Alexeivitch |author1-link=Peter Kropotkin|last2= Bealby |first2=John Thomas| pages = 193&ndash;195 |short= 1}} * [http://earthfromspace.photoglobe.info/spc_volga_delta.html خلا مان وولگا ڊيلٽا] * [http://as-volga.com وولگا ساحلن جون تصويرون] * [https://www.youtube.com/watch?v=la1gakAbIgw وولگا جي ماخذ بابت وڊيو] * [http://earthfromspace.photoglobe.info/spc_volga_delta.html Volga Delta from Space] * [http://as-volga.com Photos of the Volga coasts] * [https://www.youtube.com/watch?v=la1gakAbIgw Video about the source of the Volga] {{Authority control}} [[زمرو:وولگا درياهه]] [[زمرو:روس]] [[زمرو:دریاھہ ۽ نديون]] [[زمرو:پيچدار درياهه]] [[زمرو:چوواشيا جا درياهه]] [[زمرو:ڪالميڪيا جا درياهه]] [[زمرو:تاتارستان جا درياهه]] [[زمرو:روس ۾ درياهه ۽ نديون]] [[زمرو:روس ۾ پيچدار درياهه]] [[زمرو:ٽوير اوبلاسٽ جا درياهه]] [[زمرو:سمارا اوبلاسٽ جا درياهه]] [[زمرو:ساراتو اوبلاسٽ جا درياهه]] [[زمرو:آسٽراخان اوبلاسٽ جا درياهه]] [[زمرو:ڪوسٽروما اوبلاسٽ جا درياهه]] [[زمرو:وولگوگراڊ اوبلاسٽ جا درياهه]] [[زمرو:ياروسلاول اوبلاسٽ جا درياهه]] [[زمرو:نزني نووگوروڊ اوبلاسٽ جا درياهه]] [[زمرو:ڪيسپين سمنڊ جون مددگار نديون]] i47r2taobvna57vcw709p0c1nh6vajh 0 90722 371837 357469 2026-04-16T20:38:23Z Ibne maryam 17680 removed [[Category:پروسيسر]]; added [[Category:ڪمپيوٽر سسٽم]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371837 wikitext text/x-wiki {{Infobox computer hardware | name = سينٽرل پروسيسنگ يونٽ (CPU) | image = [[File:Intel 80486DX2 bottom.jpg|250px]] | caption = هڪ انٽيل 80486DX2 مائڪرو پروسيسر جو هيٺيون حصو. | inventor = فيڊريڪو فيگن، مارڪين هاف، مساتوشي شيما | type = پروسيسر | function = ڪمپيوٽر پروگرام جي هدايتن تي عمل ڪرڻ }} '''سينٽرل پروسيسنگ يونٽ''' (Central Processing Unit) يا '''سي پي يو''' (CPU)، جنھن کي مين پروسيسر پڻ چيو ويندو آهي، [[ڪمپيوٽر]] جو اهو برقي سرڪٽ آهي جيڪو ڪمپيوٽر پروگرام جي هدايتن تي عمل ڪري ٿو. ان ۾ رياضي (Arithmetic)، منطق (Logic)، ڪنٽرولنگ، ۽ ان پٽ/آئوٽ پٽ (I/O) آپريشنز شامل آهن. == بنيادي حصا ۽ ڪم ڪرڻ جو طريقو == جيتوڻيڪ وقت سان گڏ سي پي يو جي بناوٽ تبديل ٿي آهي، پر ان جا بنيادي حصا ساڳيا رهيا آهن: * '''ارٿميٽڪ لاجڪ يونٽ (ALU):''' هي حصو تمام رياضي واريون حساب ڪتاب ۽ منطقي آپريشنز سرانجام ڏئي ٿو. * '''ڪنٽرول يونٽ (CU):''' هي حصو ميموري مان هدايتون حاصل ڪرڻ (Fetching)، انهن کي سمجهڻ (Decoding) ۽ عمل ڪرائڻ (Execution) جي عمل جي نگراني ڪري ٿو. * '''رجسٽرز (Registers):''' اهي پروسيسر جي اندر ئي تمام تيز ميموري هوندا آهن جيڪي عارضي طور تي ڊيٽا ذخيرو ڪندا آهن. == جديد پروسيسرز ۽ ٽيڪنالاجي == * '''ملٽي ڪور پروسيسرز (Multi-core):''' اڄڪلهه هڪ ئي چپ (IC) تي هڪ کان وڌيڪ سي پي يوز لڳل هوندا آهن، جن کي "ڪور" (Cores) چيو ويندو آهي. هي ڪمپيوٽر جي رفتار کي وڌائڻ ۾ مدد ڪن ٿا. * '''ڪيش ميموري (Cache):''' جديد سي پي يوز جو هڪ وڏو حصو "ڪيش" ميموريءَ لاءِ وقف هوندو آهي ته جيئن بار بار استعمال ٿيندڙ ڊيٽا کي تيزيءَ سان پروسيس ڪري سگهجي. * '''سسٽم آن چپ (SoC):''' جڏهن هڪ ئي چپ تي سي پي يو، ميموري، ۽ ٻيا حصا (جهڙوڪ گرافڪس) موجود هجن، ته ان کي SoC يا مائڪرو ڪنٽرولر چيو ويندو آهي، جيڪي اڪثر اسمارٽ فونز ۾ استعمال ٿين ٿا. == سي پي يو بمقابله جي پي يو (GPU) == سي پي يو عام مقصدي ڪمن لاءِ هوندو آهي، جڏهن ته '''گرافڪس پروسيسنگ يونٽ''' (GPU) خاص طور تي تصويرن، وڊيوز ۽ گرافڪس جي تيز پروسيسنگ لاءِ ٺاهيو ويندو آهي. == وڌيڪ ڏسو == * [[مائڪرو پروسيسر]] * [[ڪمپيوٽر هارڊويئر]] * [[ميموري]] == حوالا == {{حوالا}} [[زمرو:ڪمپيوٽر هارڊويئر]] [[زمرو:ڪمپيوٽر سسٽم]] [[زمرو:ڪمپيوٽر آرڪيٽيڪچر]] 557svhri5q5c4pxcyrtgkmnqz9i4bng 371838 371837 2026-04-16T20:40:19Z Ibne maryam 17680 371838 wikitext text/x-wiki {{Infobox computer hardware | name = سينٽرل پروسيسنگ يونٽ (CPU) | image = [[File:Intel 80486DX2 bottom.jpg|250px]] | caption = هڪ انٽيل 80486DX2 مائڪرو پروسيسر جو هيٺيون حصو. | inventor = فيڊريڪو فيگن، مارڪين هاف، مساتوشي شيما | type = پروسيسر | function = ڪمپيوٽر پروگرام جي هدايتن تي عمل ڪرڻ }} '''سينٽرل پروسيسنگ يونٽ''' (Central Processing Unit) يا '''سي پي يو''' (CPU)، جنھن کي مين پروسيسر پڻ چيو ويندو آهي، [[ڪمپيوٽر]] جو اهو برقي سرڪٽ آهي جيڪو ڪمپيوٽر پروگرام جي هدايتن تي عمل ڪري ٿو. ان ۾ رياضي (Arithmetic)، منطق (Logic)، ڪنٽرولنگ، ۽ ان پٽ/آئوٽ پٽ (I/O) آپريشنز شامل آهن. == بنيادي حصا ۽ ڪم ڪرڻ جو طريقو == جيتوڻيڪ وقت سان گڏ سي پي يو جي بناوٽ تبديل ٿي آهي، پر ان جا بنيادي حصا ساڳيا رهيا آهن: * '''ارٿميٽڪ لاجڪ يونٽ (ALU):''' هي حصو تمام رياضي واريون حساب ڪتاب ۽ منطقي آپريشنز سرانجام ڏئي ٿو. * '''ڪنٽرول يونٽ (CU):''' هي حصو ميموري مان هدايتون حاصل ڪرڻ (Fetching)، انهن کي سمجهڻ (Decoding) ۽ عمل ڪرائڻ (Execution) جي عمل جي نگراني ڪري ٿو. * '''رجسٽرز (Registers):''' اهي پروسيسر جي اندر ئي تمام تيز ميموري هوندا آهن جيڪي عارضي طور تي ڊيٽا ذخيرو ڪندا آهن. == جديد پروسيسرز ۽ ٽيڪنالاجي == * '''ملٽي ڪور پروسيسرز (Multi-core):''' اڄڪلهه هڪ ئي چپ (IC) تي هڪ کان وڌيڪ سي پي يوز لڳل هوندا آهن، جن کي "ڪور" (Cores) چيو ويندو آهي. هي ڪمپيوٽر جي رفتار کي وڌائڻ ۾ مدد ڪن ٿا. * '''ڪيش ميموري (Cache):''' جديد سي پي يوز جو هڪ وڏو حصو "ڪيش" ميموريءَ لاءِ وقف هوندو آهي ته جيئن بار بار استعمال ٿيندڙ ڊيٽا کي تيزيءَ سان پروسيس ڪري سگهجي. * '''سسٽم آن چپ (SoC):''' جڏهن هڪ ئي چپ تي سي پي يو، ميموري، ۽ ٻيا حصا (جهڙوڪ گرافڪس) موجود هجن، ته ان کي SoC يا مائڪرو ڪنٽرولر چيو ويندو آهي، جيڪي اڪثر اسمارٽ فونز ۾ استعمال ٿين ٿا. == سي پي يو بمقابله جي پي يو (GPU) == سي پي يو عام مقصدي ڪمن لاءِ هوندو آهي، جڏهن ته '''گرافڪس پروسيسنگ يونٽ''' (GPU) خاص طور تي تصويرن، وڊيوز ۽ گرافڪس جي تيز پروسيسنگ لاءِ ٺاهيو ويندو آهي. == وڌيڪ ڏسو == * [[مائڪرو پروسيسر]] * [[ڪمپيوٽر هارڊويئر]] * [[ميموري]] ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Commons category|Central processing units}} {{Wikiversity|Introduction to Computers/Processor}} * {{HowStuffWorks|microprocessor|How Microprocessors Work}}. * [https://spectrum.ieee.org/25-microchips-that-shook-the-world 25 Microchips that shook the world] – an article by the [[Institute of Electrical and Electronics Engineers]]. [[زمرو:ڪمپيوٽر هارڊويئر]] [[زمرو:ڪمپيوٽر سسٽم]] [[زمرو:ڪمپيوٽر آرڪيٽيڪچر]] i6qmr4sm0fz7bkh972zc6pte1i2ka5q 371839 371838 2026-04-16T20:48:32Z Ibne maryam 17680 371839 wikitext text/x-wiki {{Infobox computer hardware | name = سينٽرل پروسيسنگ يونٽ (CPU) | image = [[File:Intel 80486DX2 bottom.jpg|250px]] | caption = هڪ انٽيل 80486DX2 مائڪرو پروسيسر جو هيٺيون حصو. | inventor = فيڊريڪو فيگن، مارڪين هاف، مساتوشي شيما | type = پروسيسر | function = ڪمپيوٽر پروگرام جي هدايتن تي عمل ڪرڻ }} '''سينٽرل پروسيسنگ يونٽ''' (Central Processing Unit) يا '''سي پي يو''' (CPU)، جنھن کي مين پروسيسر پڻ چيو ويندو آهي، [[ڪمپيوٽر]] جو اهو برقي سرڪٽ آهي جيڪو ڪمپيوٽر پروگرام جي هدايتن تي عمل ڪري ٿو. ان ۾ رياضي (Arithmetic)، منطق (Logic)، ڪنٽرولنگ، ۽ ان پٽ/آئوٽ پٽ (I/O) آپريشنز شامل آهن. == بنيادي حصا ۽ ڪم ڪرڻ جو طريقو == جيتوڻيڪ وقت سان گڏ سي پي يو جي بناوٽ تبديل ٿي آهي، پر ان جا بنيادي حصا ساڳيا رهيا آهن: * '''ارٿميٽڪ لاجڪ يونٽ (ALU):''' هي حصو تمام رياضي واريون حساب ڪتاب ۽ منطقي آپريشنز سرانجام ڏئي ٿو. * '''ڪنٽرول يونٽ (CU):''' هي حصو ميموري مان هدايتون حاصل ڪرڻ (Fetching)، انهن کي سمجهڻ (Decoding) ۽ عمل ڪرائڻ (Execution) جي عمل جي نگراني ڪري ٿو. * '''رجسٽرز (Registers):''' اهي پروسيسر جي اندر ئي تمام تيز ميموري هوندا آهن جيڪي عارضي طور تي ڊيٽا ذخيرو ڪندا آهن. == جديد پروسيسرز ۽ ٽيڪنالاجي == * '''ملٽي ڪور پروسيسرز (Multi-core):''' اڄڪلهه هڪ ئي چپ (IC) تي هڪ کان وڌيڪ سي پي يوز لڳل هوندا آهن، جن کي "ڪور" (Cores) چيو ويندو آهي. هي ڪمپيوٽر جي رفتار کي وڌائڻ ۾ مدد ڪن ٿا. * '''ڪيش ميموري (Cache):''' جديد سي پي يوز جو هڪ وڏو حصو "ڪيش" ميموريءَ لاءِ وقف هوندو آهي ته جيئن بار بار استعمال ٿيندڙ ڊيٽا کي تيزيءَ سان پروسيس ڪري سگهجي. * '''سسٽم آن چپ (SoC):''' جڏهن هڪ ئي چپ تي سي پي يو، ميموري، ۽ ٻيا حصا (جهڙوڪ گرافڪس) موجود هجن، ته ان کي SoC يا مائڪرو ڪنٽرولر چيو ويندو آهي، جيڪي اڪثر اسمارٽ فونز ۾ استعمال ٿين ٿا. == سي پي يو بمقابله جي پي يو (GPU) == سي پي يو عام مقصدي ڪمن لاءِ هوندو آهي، جڏهن ته '''گرافڪس پروسيسنگ يونٽ''' (GPU) خاص طور تي تصويرن، وڊيوز ۽ گرافڪس جي تيز پروسيسنگ لاءِ ٺاهيو ويندو آهي. == وڌيڪ ڏسو == * [[مائڪرو پروسيسر]] * [[ڪمپيوٽر هارڊويئر]] * [[ميموري]] ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Commons category|Central processing units}} {{Wikiversity|Introduction to Computers/Processor}} * {{HowStuffWorks|microprocessor|How Microprocessors Work}}. * [https://spectrum.ieee.org/25-microchips-that-shook-the-world 25 Microchips that shook the world] – an article by the [[Institute of Electrical and Electronics Engineers]]. [[زمرو:سينٽرل پراسيسنگ يونٽ]] [[زمرو:ڪمپيوٽر]] [[زمرو:اليڪٽرانڪ جزا]] [[زمرو:ڪمپيوٽر هارڊويئر]] [[زمرو:ڊجيٽل سسٽم]] [[زمرو:ڪمپيوٽر سسٽم]] [[زمرو:بنيادي ڪمپيوٽر جزا]] [[زمرو:ڊجيٽل اليڪٽرانڪس]] [[زمرو:سي پي يو ٽيڪنالاجيون]] [[زمرو:اليڪٽرانڪ ڊيزائن]] [[زمرو:اليڪٽرانڪ ڊيزائن آٽوميشن]] 2vv5u186uinwpoqd5hvsa99vqlhm7l1 0 91706 371860 360732 2026-04-17T06:51:46Z Ziv 19611 ([[c:GR|GR]]) [[File:Caravaggio - The Incredulity of Saint Thomas.jpg]] → [[File:Caravaggio incredulity.jpg]] → File replacement: Updating from an old and lower-quality version to a newer version with better quality ([[c:c:GR]]) 371860 wikitext text/x-wiki {{Short description|يقين ۽ بي يقيني جي وچ واري حالت}} {{emotion}} '''شڪ''' (Doubt) هڪ اهڙي [[ذهني حالت]] آهي جنهن ۾ [[دماغ]] ٻن يا ٻن کان وڌيڪ [[تضاد|متضاد]] دعوائن جي وچ ۾ لٽڪيل رهندو آهي ۽ انهن بابت [[يقين|بي يقين]] هوندو آهي.<ref name=Cath>{{Cite news | first = Alfred | last = Sharpe | title = Doubt | url = http://www.newadvent.org/cathen/05141a.htm | work = The Catholic Encyclopedia | publisher = Robert Appleton | location = New York | access-date = 2008-10-21 | quote = A state in which the mind is suspended between two contradictory propositions and unable to assent to either of them. }}</ref> جذباتي سطح تي، شڪ جو مطلب [[اعتبار|يقين]] ۽ [[بي اعتباري]] جي وچ ۾ فيصلو نه ڪري سگهڻ جي ڪيفيت آهي. ان ۾ [[غير يقيني صورتحال]]، [[بي اعتباري]] يا ڪنهن خاص [[حقيقت]]، عمل يا فيصلي تي پختي يقين جي کوٽ شامل ٿي سگهي ٿي. == نفسيات (Psychology) == نفسياتي طور تي، ڪنهن عمل جي وقفي وقفي سان ملندڙ ناڪاري نتيجن يا ردعمل جي ڪري انسان جي ذهن ۾ خوف ۽ شڪ جو ماحول پيدا ٿي سگهي ٿو.<ref name=braiker>{{Cite book|title=Who's Pulling Your Strings ? |first=Harriet B.|last=Braiker |year=2004 |publisher=McGraw Hill Professional}}</ref> == فلسفو (Philosophy) == [[رينيه ڊيڪارٽ]] پنهنجي بنيادي فلسفيانه تحقيقات ۾ "ڊيڪارٽي شڪ" (Cartesian doubt) کي هڪ اهم طريقي طور استعمال ڪيو. فلسفي جون شاخون جهڙوڪ [[منطق]] (Logic)، شڪي ڳالهين، [[احتمال]] (Probability) ۽ يقيني حقيقتن جي وچ ۾ فرق ڪرڻ تي زور ڏين ٿيون. [[لوڊوگ وٽگنسٽائن]] پنهنجي ڪتاب ''On Certainty'' ۾ بيان ڪيو آهي ته 'شڪ' ۽ 'يقين' جا لفظ اسان جي روزاني زندگيءَ ۾ هڪٻئي سان ائين ڳنڍيل آهن جو جيڪڏهن اسان ڪنهن حقيقت بابت يقين نٿا رکي سگهون، ته پوءِ اسان پنهنجي لفظن جي معنيٰ بابت به يقين نٿا رکي سگهون. == الاهيات يا مذهب (Theology) == [[فائل:Caravaggio incredulity.jpg|thumb|left|180px|''The Incredulity of Saint Thomas'' از ڪاراوگيو.]] [[فائل:Rae, Henrietta - Doubts - 1886.jpg|thumb|180px|''Doubts'' (شڪ)، پاران هينريٽا ري، 1886ع]] مذهبي طور تي شڪ کي ڪڏهن ڪڏهن گهري ايمان تائين پهچڻ جو رستو سمجهيو ويندو آهي، جهڙوڪ حضرت توما (St. Thomas) جو قصو. ڪجهه مذهبي مفڪرن موجب، حقيقي ايمان تڏهن ئي ممڪن آهي جڏهن انسان شڪ جي مرحلي مان گذري پنهنجي عقل کي مطمئن ڪري. خدا جي وجود بابت شڪ [[لادينيت]] (Agnosticism) جو بنياد بڻجي سگهي ٿو. ٻئي طرف، [[سورين ڪيئرڪيگارڊ]] جهڙن مسيحي وجودي مفڪرن جو خيال آهي ته خدا تي سچو ايمان رکڻ لاءِ انسان کي پنهنجي عقيدن تي شڪ ڪرڻ جي به ضرورت آهي، ڇاڪاڻ ته شڪ عقل جو حصو آهي جيڪو ثبوتن کي توري تڪي ٿو. == قانون (Law) == قانوني نظام ۾، خاص طور تي فوجداري ڪيسن ۾، پراسيڪيوشن کي پنهنجو ڪيس "معقول شڪ کان مٿانهون" ([[Beyond a reasonable doubt]]) ثابت ڪرڻو پوندو آهي. ان جو مطلب اهو آهي ته جيڪڏهن ڪنهن عام سمجهه واري ماڻهوءَ (Reasonable person) جي ذهن ۾ جوابدار جي ڏوهه بابت ڪو معقول شڪ موجود آهي، ته پوءِ کيس سزا نٿي ڏئي سگهجي. == سائنس (Science) == سائنسي طريقو (Scientific method) باقاعدي طور تي شڪ جي مقدار کي طئي ڪري ٿو ته جيئن اهو معلوم ڪري سگهجي ته آيا "وڌيڪ تحقيق جي ضرورت آهي". [[اسحاق آسيموف]] سائنس کي هڪ اهڙي نظام طور بيان ڪيو جيڪو ذهين شڪ پيدا ڪري ٿو ۽ پوءِ ان کي حل ڪري ٿو.<ref>{{Cite web |url=http://patduffyhutcheon.com/humanist%20articles/asimov.htm |title=Isaac Asimov: A Prophet for Our Time}}</ref> [[ڪارل پاپپر]] سائنسي شڪ کي هڪ ضروري اوزار طور استعمال ڪيو. هن جي نظريي موجب، سائنسدانن کي هر نظريي تي ايترو شڪ ڪرڻ گهرجي جو هو ان کي غلط ثابت ڪرڻ ([[Falsifiability]]) جي ڪوشش ڪن، ته جيئن رڳو مضبوط حقيقتون ئي بچي سگهن. == حوالا == {{حوالا}} coroynbi98gz25zq5263bgp70kidbcy 14 94930 371850 371457 2026-04-16T21:06:51Z Ibne maryam 17680 371850 wikitext text/x-wiki [[زمرو:ڪمپيوٽر]] [[زمرو:ٽيڪنالاجي]] 5p4eav1d4zbmr0wywmytbr3a68zoge6 14 95014 371799 371798 2026-04-16T11:59:54Z Memon2025 21315 371799 wikitext text/x-wiki [[زمرو:پاڪستان جا تعليمي ادارا]] [[زمرو:پاڪستان ۾ ڪمپيوٽر سائنس جي تعليم]] scbq78cd07adc2iyttzdr6vetkwja8g 0 95015 371805 2026-04-16T17:25:00Z Ibne maryam 17680 نئون صفحو: هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو... 371805 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي. ohkhaalyxld32nndnms3hv3rwhsv9hm 371806 371805 2026-04-16T17:25:34Z Ibne maryam 17680 added [[Category:ڪمپيوٽر سائنس]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371806 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي. [[زمرو:ڪمپيوٽر سائنس]] h11d5oo356qk7vcgev9o7wp2i8i60bw 371807 371806 2026-04-16T17:26:10Z Ibne maryam 17680 added [[Category:بولين الجبرا]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371807 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي. [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] lgtjemi0qv3kel0c35k5lir9frgce89 371808 371807 2026-04-16T17:26:42Z Ibne maryam 17680 added [[Category:الگورٿم]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371808 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي. [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] [[زمرو:الگورٿم]] stqe9lwqbqbnb533tsfgz4s5n9aeea7 371811 371808 2026-04-16T19:16:17Z Ibne maryam 17680 371811 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي. {{Short description|Device performing a Boolean function}} {{Redirect|Discrete logic|discrete circuitry|Discrete circuit|discrete TTL logic|Transistor–transistor logic|the former image processing company|Discreet Logic}} {{Use dmy dates|date=September 2022|cs1-dates=y}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] A '''logic gate''' is a device that performs a [[Boolean function]], a [[logical operation]] performed on one or more [[Binary number|binary]] inputs that produces a single binary output. Depending on the context, the term may refer to an '''ideal logic gate''', one that has, for instance, zero [[rise time]] and unlimited [[fan-out]], or it may refer to a non-ideal physical device<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> (see [[ideal and real op-amps]] for comparison). The primary way of building logic gates uses [[diode]]s or [[transistor]]s acting as [[electronic switches]]. Today, most logic gates are made from [[MOSFET]]s (metal–oxide–semiconductor [[field-effect transistor]]s).<ref name=kanellos >{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> They can also be constructed using [[vacuum tube]]s, electromagnetic [[relay]]s with [[relay logic]], [[fluidic logic]], [[pneumatics#Pneumatic logic|pneumatic logic]], [[optics]], [[molecular logic gate|molecules]], acoustics,<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> or even [[Analytical Engine|mechanical]] or thermal<ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> elements. Logic gates can be cascaded in the same way that Boolean functions can be composed, allowing the construction of a physical model of all of [[Boolean logic]], and therefore, all of the algorithms and [[mathematics]] that can be described with Boolean logic. '''Logic circuits''' include such devices as [[multiplexer]]s, [[processor register|registers]], [[arithmetic logic unit]]s (ALUs), and [[computer memory]], all the way up through complete [[microprocessor]]s,<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> which may contain more than 100 million logic gates. Compound logic gates [[AND-OR-invert]] (AOI) and [[OR-AND-invert]] (OAI) are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> There are seven basic logic gates: [[NOT gate|NOT]], [[OR gate|OR]], [[NOR gate|NOR]] (Negation of the OR statement), [[AND gate|AND]], [[NAND gate|NAND]] (Negation of the AND statement), [[XOR gate|XOR]] (Exclusive OR), [[XNOR gate|XNOR]] (Negation of the Exclusive OR statement).<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == History and development == The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:عددي نظام]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 6971ej8dmvf1fxyvafpxash1pekypbm 371812 371811 2026-04-16T19:18:13Z Ibne maryam 17680 removed [[Category:عددي نظام]]; added [[Category:رياضيات]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371812 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي. {{Short description|Device performing a Boolean function}} {{Redirect|Discrete logic|discrete circuitry|Discrete circuit|discrete TTL logic|Transistor–transistor logic|the former image processing company|Discreet Logic}} {{Use dmy dates|date=September 2022|cs1-dates=y}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] A '''logic gate''' is a device that performs a [[Boolean function]], a [[logical operation]] performed on one or more [[Binary number|binary]] inputs that produces a single binary output. Depending on the context, the term may refer to an '''ideal logic gate''', one that has, for instance, zero [[rise time]] and unlimited [[fan-out]], or it may refer to a non-ideal physical device<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> (see [[ideal and real op-amps]] for comparison). The primary way of building logic gates uses [[diode]]s or [[transistor]]s acting as [[electronic switches]]. Today, most logic gates are made from [[MOSFET]]s (metal–oxide–semiconductor [[field-effect transistor]]s).<ref name=kanellos >{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> They can also be constructed using [[vacuum tube]]s, electromagnetic [[relay]]s with [[relay logic]], [[fluidic logic]], [[pneumatics#Pneumatic logic|pneumatic logic]], [[optics]], [[molecular logic gate|molecules]], acoustics,<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> or even [[Analytical Engine|mechanical]] or thermal<ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> elements. Logic gates can be cascaded in the same way that Boolean functions can be composed, allowing the construction of a physical model of all of [[Boolean logic]], and therefore, all of the algorithms and [[mathematics]] that can be described with Boolean logic. '''Logic circuits''' include such devices as [[multiplexer]]s, [[processor register|registers]], [[arithmetic logic unit]]s (ALUs), and [[computer memory]], all the way up through complete [[microprocessor]]s,<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> which may contain more than 100 million logic gates. Compound logic gates [[AND-OR-invert]] (AOI) and [[OR-AND-invert]] (OAI) are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> There are seven basic logic gates: [[NOT gate|NOT]], [[OR gate|OR]], [[NOR gate|NOR]] (Negation of the OR statement), [[AND gate|AND]], [[NAND gate|NAND]] (Negation of the AND statement), [[XOR gate|XOR]] (Exclusive OR), [[XNOR gate|XNOR]] (Negation of the Exclusive OR statement).<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == History and development == The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 6q7si0n0j53uq2le6v65168710euuq1 371813 371812 2026-04-16T19:48:14Z Ibne maryam 17680 371813 wikitext text/x-wiki هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> {{Short description|Device performing a Boolean function}} {{Redirect|Discrete logic|discrete circuitry|Discrete circuit|discrete TTL logic|Transistor–transistor logic|the former image processing company|Discreet Logic}} {{Use dmy dates|date=September 2022|cs1-dates=y}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == تاريخ ۽ ترقي == == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == History and development == The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] inhelhwcltaedjlygwn7v5x81pfudsu 371814 371813 2026-04-16T19:51:06Z Ibne maryam 17680 371814 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == تاريخ ۽ ترقي == == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == History and development == The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] irb9bp99izir28q68oizpi9tb2xxpsx 371815 371814 2026-04-16T19:52:45Z Ibne maryam 17680 371815 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == تاريخ ۽ ترقي == == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == History and development == The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] djmjazkesa2rpeffm9tjmqfuzjzrhr9 371816 371815 2026-04-16T19:55:08Z Ibne maryam 17680 371816 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == تاريخ ۽ ترقي == == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == History and development == The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 8cjbzfroxsujxapmykqroe17on669l6 371817 371816 2026-04-16T19:55:59Z Ibne maryam 17680 371817 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> == تاريخ ۽ ترقي == == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] j9xrh1t6h4dancoz7k9q1nm1urtcimj 371818 371817 2026-04-16T19:56:44Z Ibne maryam 17680 /* تاريخ ۽ ترقي */ 371818 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705), influenced by the ancient ''[[I Ching]]''{{'}}s binary system.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> Leibniz established that using the binary system combined the principles of [[arithmetic]] and [[logic]]. The [[analytical engine]] devised by [[Charles Babbage]] in 1837 used mechanical logic gates based on gears.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> Early [[Electromechanical computer]]s were constructed from [[switch]]es and [[relay logic]] rather than the later innovations of [[vacuum tube]]s (thermionic valves) or [[transistor]]s (from which later electronic computers were constructed). [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]],<ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935 to 1938). From 1934 to 1936, [[NEC]] engineer [[Akira Nakashima]], [[Claude Shannon]] and [[Victor Shestakov]] introduced [[switching circuit theory]] in a series of papers showing that [[Two-element Boolean algebra|two-valued]] [[Boolean algebra]], which they discovered independently, can describe the operation of switching circuits.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digital [[computer]]s. Switching circuit theory became the foundation of [[digital circuit]] design, as it became widely known in the electrical engineering community during and after [[World War II]], with theoretical rigor superseding the ''ad hoc'' methods that had prevailed previously.<ref name="Stanković-Astola_2008"/> In 1948, [[John Bardeen|Bardeen]] and [[Walter Houser Brattain|Brattain]] patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> In 1957, Frosch and Derick were able to manufacture [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]] planar gates.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> Both types were later combined and adapted into [[complementary MOS]] (CMOS) logic by [[Chih-Tang Sah]] and [[Frank Wanlass]] at [[Fairchild Semiconductor]] in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 1ix6l9wvjd5hn6bsspognd6czqe3vy6 371819 371818 2026-04-16T20:20:11Z Ibne maryam 17680 371819 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Symbols <!--This section is linked from [[Schematic]]: do not rename heading without including an anchor to previous name ([[MOS:HEAD]])--> == [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] fo1e97tuy83nsng4krlurtz9aicw0w1 371820 371819 2026-04-16T20:20:56Z Ibne maryam 17680 371820 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> == علامتون == == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] fix7rr00fqk4767pp3n2jr9pgaf8tjd 371821 371820 2026-04-16T20:21:52Z Ibne maryam 17680 371821 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == De Morgan equivalent symbols == By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] leje414ry8hmxu2bqv8zfhed4fikzjj 371822 371821 2026-04-16T20:22:21Z Ibne maryam 17680 371822 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} == ڊي مورگن جي برابر علامتون == == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] s9wfvi34adaed8a4aoxxs173y8wq31f 371823 371822 2026-04-16T20:23:05Z Ibne maryam 17680 /* ڊي مورگن جي برابر علامتون */ 371823 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Truth tables == Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] hu5xn051g2un2czbbzav6grtz3iail1 371824 371823 2026-04-16T20:23:36Z Ibne maryam 17680 371824 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. == ٽرٿ ٽيبل (Truth Tables) == == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] pezgpx3oxiidex0ggzzuxzjrzhg0khk 371825 371824 2026-04-16T20:24:30Z Ibne maryam 17680 /* ٽرٿ ٽيبلز */ 371825 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Universal logic gates == {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 4mfufkcekx6u98wdqdj7cu2oan6s2r0 371826 371825 2026-04-16T20:25:05Z Ibne maryam 17680 371826 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} == يونيورسل لاجڪ گيٽس == == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 797t10b916o423qt0x5jauizb0p3mxi 371827 371826 2026-04-16T20:25:52Z Ibne maryam 17680 /* يونيورسل لاجڪ گيٽس */ 371827 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] == Data storage and sequential logic == [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] {{Main|Sequential logic}} Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] t4rk0owvz01zsair0mi7xx9qn9qxek3 371828 371827 2026-04-16T20:26:28Z Ibne maryam 17680 371828 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} == ڊيٽا اسٽوريج ۽ ترتيب وار منطق == == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] r5igc8z6covds7jwj1lp0i1wydt4mf4 371829 371828 2026-04-16T20:27:33Z Ibne maryam 17680 /* ڊيٽا اسٽوريج ۽ ترتيب وار منطق */ 371829 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. == پڻ ڏسو == # بولين الجبرا # ڊجيٽل سرڪٽ # انٽيگريٽڊ سرڪٽ # پروسيسر # ٽرٿ ٽيبل # [[ڪمپيوٽنگ]] ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] rggi01mx2395nvde9iq36f8dihjhwf3 371830 371829 2026-04-16T20:28:34Z Ibne maryam 17680 371830 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== {{div col|colwidth=22em}} * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Digital circuit]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Truth table]] * [[Unconventional computing]] {{div col end}} ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 5sc5v1bhozzg23nb9dmezwt00ob9d9j 371831 371830 2026-04-16T20:31:21Z Ibne maryam 17680 371831 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== {{Wikiversity|لاجڪ گيٽ}} * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] qdmf0iq6y29pyyoccodyssasx5amhov 371832 371831 2026-04-16T20:32:15Z Ibne maryam 17680 371832 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:رياضيات]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:بولين الجبرا]] 1gd2van07hlsb65k8cmg79s10ppze1h 371833 371832 2026-04-16T20:33:48Z Ibne maryam 17680 371833 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] [[زمرو:ڪمپيوٽر سائنس]] nefw0qnmw0tvxwydsliks3rl1xxfoxm 371835 371833 2026-04-16T20:35:29Z Ibne maryam 17680 added [[Category:ڪمپيوٽر انجنيئرنگ]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371835 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر انجنيئرنگ]] rn82a3wb6o8h8cm8trpa7xfa90mwde3 371836 371835 2026-04-16T20:36:47Z Ibne maryam 17680 added [[Category:ڪمپيوٽر سسٽم]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371836 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر انجنيئرنگ]] [[زمرو:ڪمپيوٽر سسٽم]] bxtg1y7mkcwu5hattbd50lxmsi44m64 371858 371836 2026-04-17T06:43:51Z Ibne maryam 17680 /* ٻاهريان ڳنڍڻا */ 371858 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|A logic circuit diagram for a 4-bit [[Carry-lookahead adder|carry lookahead binary adder]] design using only the [[AND gate|AND]], [[OR gate|OR]], and [[XOR gate|XOR]] logic gates|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:لاجڪ گيٽس]] [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر انجنيئرنگ]] [[زمرو:ڪمپيوٽر سسٽم]] m91mprt2mcutcmleft0u5lwwxi2c4eo 371859 371858 2026-04-17T06:47:29Z Ibne maryam 17680 371859 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|صرف AND، OR، ۽ XOR لاجڪ گيٽس استعمال ڪندي 4-بٽ لُڪ اَهيڊ بائنري ايڊر ڊيزائن لاءِ هڪ لاجڪ سرڪٽ ڊاگرام.|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A synchronous 4-bit up/down [[decade counter]] symbol (74LS192) in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 60617-12 [missing "C3" at pin 11]|class=skin-invert-image]] There are two sets of symbols for elementary logic gates in common use, both defined in [[ANSI]]/[[IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives from [[United States Military Standard]] MIL-STD-806 of the 1950s and 1960s.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> The IEC standard, [[IEC]] 60617-12, has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe, [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom, and [[DIN]] EN 60617-12:1998 in Germany. The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor. IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another. In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]]. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:لاجڪ گيٽس]] [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر انجنيئرنگ]] [[زمرو:ڪمپيوٽر سسٽم]] 5zpa9azz5ipgtlrzjz17vuqh3abbyf7 371861 371859 2026-04-17T07:22:30Z Ibne maryam 17680 371861 wikitext text/x-wiki {{Short description|Device performing a Boolean function}} [[File:Four bit adder with carry lookahead.svg|thumb|صرف AND، OR، ۽ XOR لاجڪ گيٽس استعمال ڪندي 4-بٽ لُڪ اَهيڊ بائنري ايڊر ڊيزائن لاءِ هڪ لاجڪ سرڪٽ ڊاگرام.|class=skin-invert-image]] هڪ '''لاجڪ گيٽ''' (Logic Gate) هڪ اھڙو ڊوائيس (عام طور تي مختلف قسمن جي ٽرانزسٽرن جو مجموعو) آهي جيڪو هڪ بولين فنڪشن، هڪ يا وڌيڪ بائنري ان پٽ تي ڪيل هڪ منطقي آپريشن، جيڪو هڪ واحد بائنري آئوٽ پُٽ پيدا ڪري ٿو، انجام ڏئي ٿو. تناظر تي منحصر ڪري ٿي، ته اصطلاح هڪ مثالي لاجڪ گيٽ جو حوالو ڏئي سگهي ٿي، هڪ جن ۾، مثال طور، صفر اڀرڻ جو وقت ۽ لامحدود فين آئوٽ يا اها هڪ غير مثالي جسماني ڊوائيس جو حوالو ڏئي سگهي ٿي.<ref>{{cite book |author=Jaeger |title=Microelectronic Circuit Design |publisher=[[McGraw-Hill]] |date=1997 |isbn=0-07-032482-4 |pages=226–233}}</ref> لاجڪ گيٽس ٺاهڻ جو بنيادي طريقو ڊائيوڊ ٽيوب يا ٽرانزسٽر استعمال ڪندي آهي جيڪا اليڪٽرانڪ سوئچ طور ڪم ڪندا آهن. اڄڪلهه، گھڻا لاجڪ گيٽس "<small>ميٽل-آڪسائيڊ-سيمي ڪنڊڪٽر فيلڊ-اثر ٽرانزسٽر</small>" <small>(MOSFETs)</small> <small>مان ٺهيل آهن</small>.<ref name="kanellos">{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}} ''From [[Integrated circuit]]''</ref> انهن کي ويڪيوم ٽيوب، ريلي لاجڪ سان برقي مقناطيسي ريلي، فلوئڊ لاجڪ، نيوميٽڪ لاجڪ، آپٽڪس، صوتيات<ref>{{citation |url=https://pubs.aip.org/aip/apl/article-abstract/106/11/113503/27163/Acoustic-logic-gates-and-Boolean-operation-based?redirectedFrom=fulltext |title=Acoustic logic gates and Boolean operation based on self-collimating acoustic beams |date=2015 |doi=10.1063/1.4915338 |access-date=2024-08-17 |last1=Zhang |first1=Ting |last2=Cheng |first2=Ying |last3=Guo |first3=Jian-Zhong |last4=Xu |first4=Jian-yi |last5=Liu |first5=Xiao-jun |journal=Applied Physics Letters |volume=106 |issue=11 |article-number=113503 |bibcode=2015ApPhL.106k3503Z |url-access=subscription }}</ref> يا اڃا به ميڪاني يا ٿرمل طريقن سان پڻ ٺاهي سگهجي ٿو. <ref>{{cite journal | url=https://journals.aps.org/prl/abstract/10.1103/PhysRevLett.99.177208 | doi=10.1103/PhysRevLett.99.177208 | title=Thermal Logic Gates: Computation with Phonons | date=2007 | last1=Wang | first1=Lei | last2=Li | first2=Baowen | journal=Physical Review Letters | volume=99 | issue=17 | article-number=177208 | pmid=17995368 | arxiv=0709.0032 | bibcode=2007PhRvL..99q7208W | s2cid=10934270 }}</ref> لاجڪ گيٽ کي ساڳئي طريقي سان ڪاسڪيڊ ڪري سگهجي ٿو،جيئن بولين فنڪشن ٺاهي سگهجن ٿا، سڀني بولين لاجڪ جي طبعي ماڊل جي تعمير جي اجازت ڏئي ٿي ۽ تنهن ڪري، سڀئي [[الگورٿم]] ۽ [[رياضي]] جيڪي بولين لاجڪ سان بيان ڪري سگهجن ٿا. لاجڪ سرڪٽس ۾ ملٽي پلڪسرز، رجسٽر، رياضي منطق يونٽ (ALUs) ۽ ڪمپيوٽر ميموري جهڙا ڊوائيس شامل آهن ۽ مڪمل مائڪرو پروسيسرز ذريعي انهن ۾ 100 ملين کان وڌيڪ لاجڪ گيٽ شامل ٿي سگهن ٿا.<ref>{{cite book | url=https://books.google.com/books?id=GBVADQAAQBAJ&q=processor+logic+gates | title=Digital Systems: From Logic Gates to Processors | isbn=978-3-319-41198-9 | last1=Deschamps | first1=Jean-Pierre | last2=Valderrama | first2=Elena | last3=Terés | first3=Lluís | date=12 October 2016 | publisher=Springer }}</ref> ڪمپائونڊ لاجڪ گيٽس <small>AND-OR-invert</small> ۽ <small>OR-AND-invert</small> اڪثر ڪري سرڪٽ ڊيزائن ۾ استعمال ڪيا ويندا آهن ڇاڪاڻ ته MOSFETs استعمال ڪندي انهن جي تعمير انفرادي گيٽس جي مجموعي کان آسان ۽ وڌيڪ ڪارآمد آهي.<ref>{{cite book |title=Engineering digital design |edition=2nd |author-last=Tinder |author-first=Richard F. |date=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher=Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&q=AOI+gate&pg=PT347}}</ref> ست بنيادي لاجڪ گيٽس آهن: # NOT # OR # NOR (OR بيان جي نفي) # AND # NAND (AND بيان جي نفي) # XOR (خاص OR) # XNOR (خاص OR بيان جي نفي)<ref>https://www.sci.brooklyn.cuny.edu/~goetz/projects/logic/logic2.html</ref> ==تاريخ ۽ ترقي== [[انگن جو ڏونائي سرشتو|بائنري نمبر سسٽم]] کي گوٽفريڊ ولهيلم ليبنز (1705ع ۾ شايع ٿيل) پاران بهتر ڪيو ويو، جيڪو قديم آءِ چنگ جي [[انگن جو ڏونائي سرشتو|بائنري سسٽم]] کان متاثر هو.<ref name="Nylan2001">{{cite book |author-first=Michael |author-last=Nylan |title=The Five "Confucian" Classics |url=https://books.google.com/books?id=KykM1DhBxd8C&pg=PA206 |access-date=2010-06-08 |date=2001 |publisher=[[Yale University Press]] |isbn=978-0-300-08185-5 |pages=204–206}}</ref><ref name="binary">{{cite book |author-first=Franklin |author-last=Perkins |title=Leibniz and China: A Commerce of Light |publisher=[[Cambridge University Press]] |date=2004 |isbn= 978-0-521-83024-9|pages=117 |chapter=Exchange with China |chapter-url=https://books.google.com/books?id=0Jzv9IoAHFsC&dq=117&pg=PA117 |quote=... one of the traditional orderings of the hexagrams, the ''xiantian tu'' ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.}}</ref> ليبنز قائم ڪيو ته بائنري سسٽم استعمال ڪرڻ سان [[علم رياضيات|رياضي]] ۽ [[منطق]] جا اصول گڏ ٿين ٿا. سال 1837ع ۾ چارلس بيبيج پاران تيار ڪيل تجزياتي انجن گيئرز تي ٻڌل ميڪنيڪل لاجڪ گيٽ استعمال ڪيا ويا.<ref>{{cite book |url=https://books.google.com/books?id=FCjOBgAAQBAJ&dq=Babbage+Logic+Gate&pg=PA17 |title=Embedded Systems Circuits and Programming |author1=Julio Sanchez |author2=Maria P. Canton |publisher=CRC Press |date=Dec 19, 2017 |page=17|isbn=978-1-4398-7931-3 }}</ref> سال <small>1886</small>ع جي هڪ خط ۾، چارلس سينڊرز پيرس بيان ڪيو ته برقي سوئچنگ سرڪٽ ذريعي منطقي آپريشن ڪيئن ڪري سگهجن ٿا.<ref name="P2M">Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 420–423. See {{cite journal |author-link=Arthur W. Burks |author-first=Arthur W. |author-last=Burks |title=Review: Charles S. Peirce, ''The new elements of mathematics'' |journal=[[Bulletin of the American Mathematical Society]] |volume=84 |issue=5 |pages=913–918 [917] |date=1978 |doi= 10.1090/S0002-9904-1978-14533-9|url=http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145|doi-access=free }}</ref> شروعاتي برقي ميڪاني ڪمپيوٽر <small>ويڪ</small><small>يوم ٽيوب</small> (<small>ٿرميونڪ والوز</small>) يا [[ٽرانزسٽر]] (<small>جن</small><small>هن مان پوء اليڪٽرانڪ ڪمپيوٽر ٺاهيا ويا</small>) جي بعد جي جدتن جي بدران سوئچز ۽ ريلي لاجڪ مان ٺاهيا ويا هئا. لڊوگ وٽگنسٽائن 16-قطار سچائي ٽيبل جو هڪ نسخو ٽريڪٽيٽس لاجيڪو-فلسفوفس (1921ع) جي تجويز <small>5.101</small> جي طور تي متعارف ڪرايو. اتفاقي سرڪٽ جي موجد والٿر بوٿ کي <small>1924</small>ع ۾ پهرين جديد اليڪٽرانڪ <small>AND</small> گيٽ لاءِ فزڪس ۾ <small>1954</small>ع جو نوبل انعام مليو. <ref>Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.</ref> ڪونراڊ زوس پنهنجي ڪمپيوٽر "Z1" لاءِ اليڪٽروميڪينيڪل لاجڪ گيٽ ڊزائين ڪيا ۽ ٺاهيا (1935عکان 1938ع تائين). سال 1934ع کان 1936ع تائين، اين اي سي انجنيئر اڪيرا نڪاشيما، ڪلاڊ شينن ۽ وڪٽر شيسٽاڪوف هڪ سلسلي ۾ سوئچنگ سرڪٽ ٿيوري متعارف ڪرائي جنهن ۾ ڏيکاريو ويو ته ٻه قدر وارا بولين الجبرا، جيڪو انهن آزاديءَ سان دريافت ڪيو، سوئچنگ سرڪٽ جي آپريشن کي بيان ڪري سگهي ٿو.<ref>{{cite journal |title=History of Research on Switching Theory in Japan |journal=IEEJ Transactions on Fundamentals and Materials |volume=124 |issue=8 |pages=720–726 |date=2004 |doi= 10.1541/ieejfms.124.720|url=https://www.jstage.jst.go.jp/article/ieejfms/124/8/124_8_720/_article |publisher=[[Institute of Electrical Engineers of Japan]]|last1= Yamada|first1= Akihiko|bibcode=2004IJTFM.124..720Y |doi-access=free |url-access=subscription }}</ref><ref>{{cite web |title=Switching Theory/Relay Circuit Network Theory/Theory of Logical Mathematics |date= |work=IPSJ Computer Museum |publisher=[[Information Processing Society of Japan]] |url=http://museum.ipsj.or.jp/en/computer/dawn/0002.html}}</ref><ref name="historical">{{cite book |author-first1=Radomir S. |author-last1=Stanković |author-first2=Jaakko T. |author-last2=Astola |author-first3=Mark G. |author-last3=Karpovsky |citeseerx=10.1.1.66.1248 |title=Some Historical Remarks on Switching Theory |date=2007}}</ref><ref name="Stanković-Astola_2008">{{cite book |editor-first1=Radomir S.<!-- Stanislav? --> |editor-last1=Stanković |editor-link1=:de:Radomir S. Stanković |editor-first2=Jaakko Tapio |editor-last2=Astola |editor-link2=:fi:Jaakko Tapio Astola |date=2008 |isbn=978-952-15-1980-2 |issn=1456-2774 |volume=40 |issue=2 |url=http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |title=Reprints from the Early Days of Information Sciences: TICSP Series On the Contributions of Akira Nakashima to Switching Theory |series=Tampere International Center for Signal Processing (TICSP) Series |location=[[Tampere University of Technology]], Tampere, Finland |archive-url=https://web.archive.org/web/20210308002559/http://ticsp.cs.tut.fi/reports/reprint-nakashima-rr.pdf |archive-date=2021-03-08}} (3+207+1 pages) [https://web.archive.org/web/20221026175726/http://ciitlab.elfak.ni.ac.rs/predavanja/09_Nakashima.mp4 10:00 min]</ref> منطق کي لاڳو ڪرڻ لاءِ برقي سوئچ جي هن ملڪيت کي استعمال ڪرڻ بنيادي تصور آهي جيڪو سڀني اليڪٽرانڪ ڊجيٽل ڪمپيوٽرن جي بنياد آهي. سوئچنگ سرڪٽ ٿيوري ڊجيٽل سرڪٽ ڊيزائن جو بنياد بڻجي وئي، جيئن ته اها ٻي عالمي جنگ دوران ۽ بعد ۾ برقي انجنيئرنگ ڪميونٽي ۾ وڏي پيماني تي مشهور ٿي وئي، نظرياتي سختي سان ايڊهاڪ طريقن کي ختم ڪيو ويو جيڪي اڳ ۾ غالب هئا.<ref name="Stanković-Astola_2008" /> سال 1948ع ۾، بارڊين ۽ برٽين هڪ انسولٽيڊ گيٽ ٽرانزسٽر (IGFET) کي هڪ انسولٽيڊ پرت سان پيٽنٽ ڪيو. سندن تصور اڄ CMOS ٽيڪنالاجي جو بنياد بڻجي ٿو.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> 1957ع ۾، فروش ۽ ڊيرڪ <small>PMOS</small> ۽ <small>NMOS</small> پلانر گيٽ تيار ڪرڻ جي قابل هئا.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> پوء بيل ليبز جي هڪ ٽيم <small>PMOS</small> ۽ <small>NMOS</small> گيٽ سان گڏ ڪم ڪندڙ <small>MOS</small> جو مظاهرو ڪيو.<ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> ٻنهي قسمن کي بعد ۾ 1963ع ۾ فيئر چائلڊ سيمي ڪنڊڪٽر ۾ چي-ٽانگ ساه ۽ فرينڪ وانلاس پاران گڏ ڪيو ويو ۽ مڪمل MOS (CMOS) منطق ۾ ترتيب ڏنو ويو.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=[[Computer History Museum]] |access-date=6 July 2019}}</ref> ==علامتون== [[File:74LS192 Symbol.svg|thumb|right|A هڪ هم وقت ساز 4-بٽ مٿي/هيٺ (up/down) ڏهاڪي جي ڪائونٽر علامت (74LS192) ANSI/IEEE Std 91-1984 ۽ IEC اشاعت 60617-12 جي مطابق [پن 11 تي "C3" غائب آهي] |class=skin-invert-image]] عام استعمال ۾ ابتدائي لاجڪ گيٽ لاءِ علامتن جا ٻه سيٽ آهن. ٻئي <small>ANSI/IEEE Std 91-1984</small> ۾ بيان ڪيا ويا آهن ۽ ان جو اضافي <small>ANSI/IEEE Std 91a-1991</small> "مخصوص شڪل" سيٽ، روايتي اسڪيميٽڪ جي بنياد تي، سادي ڊرائنگ لاءِ استعمال ڪيو ويندو آهي ۽ <small>1950</small>ع ۽ <small>1960</small>ع جي ڏهاڪي جي گڏيل رياستن جي فوجي معيار <small>MIL-STD-806</small> مان نڪتل آهي.<ref>{{cite web |id=MIL-STD-806 |title=Graphical Symbols for Logic Diagrams |url=https://quicksearch.dla.mil/qsDocDetails.aspx?ident_number=35975 |website=ASSIST Quick Search |publisher=[[Defense Logistics Agency]] |access-date=2021-08-27}}</ref> ان کي ڪڏهن ڪڏهن غير رسمي طور تي، ان جي اصليت کي ظاهر ڪندي، "فوجي" طور بيان ڪيو ويندو آهي. "مستطيل شڪل" سيٽ (<small>ANSI</small> <small>Y32.14</small> تي ٻڌل) ۽ ٻيا ابتدائي صنعت معيار (جيئن بعد ۾ <small>IEEE</small> ۽ <small>IEC</small> پاران بهتر ڪيل) سڀني قسمن جي گيٽ لاءِ مستطيل خاڪا آهن ۽ ڊوائيسز جي تمام گهڻي وسيع رينج جي نمائندگي جي اجازت ڏيڻ ٿا (روايتي علامتن سان ممڪن کان وڌيڪ).<ref name="sdyz001a">{{cite web |title=Overview of IEEE Standard 91-1984 Explanation of Logic Symbols |date=1996 |id=SDYZ001A |publisher=Texas Instruments Semiconductor Group |url=http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf}}</ref> <small>IEC</small> معيار، <small>IEC 60617-12</small><small>،</small> ٻين معيارن پاران اختيار ڪيو ويو آهي. جهڙوڪ يورپ ۾ <small>EN 60617-12:1999</small><small>،</small> برطانيه ۾ <small>BS EN 60617-12:1999</small> ۽ جرمني ۾ <small>DIN EN 60617-12:1998.</small> <small>IEEE Std 91-1984 ۽ IEC 617-12</small> جو گڏيل مقصد <small>'''ڊجيٽل سرڪٽ'''</small> جي پيچيده منطقي ڪمن کي، اسڪيميٽڪ علامتن سان بيان ڪرڻ جو هڪجهڙائي طريقو مهيا ڪرڻ هو. اها ڪم سادي <small>AND</small> ۽ <small>OR</small> گيٽس کان وڌيڪ پيچيده هئا. اهي وچولي پيماني تي سرڪٽ، جهڙوڪ <small>'''4-بٽ'''</small> ڪائونٽر يا وڏي پيماني تي سرڪٽ جهڙوڪ مائڪرو پروسيسر تائين ٿي سگهن ٿا. <small>IEC 617-12</small> ۽ ان جو ٻيهر نمبر ٿيل جانشين <small>IEC 60617-12</small> واضح طور تي "مخصوص شڪل" علامتون نه ٿا ڏيکارين، پر انهن کان منع به نه ڪين.<ref name="sdyz001a" /> اها، بهرحال، <small>ANSI/IEEE Std 91 ۽</small> <small>91a</small> ۾ هن نوٽ سان ڏيکاريل آهن: "مخصوص شڪل جي علامت (<small>IEC</small> اشاعت <small>617</small>، حصو <small>12</small> جي مطابق) ترجيح نه آهي، پر ان معيار جي تضاد ۾ نه سمجهيو ويندو آهي." IEC 60617-12 مطابق نوٽ (سيڪشن 2.1) تي مشتمل آهي؛ "جيتوڻيڪ غير ترجيح ڏني وئي آهي. سرڪاري قومي معيارن پاران تسليم ٿيل ٻين علامتن جو استعمال (يعني علامتن جي جاءِ تي مخصوص شڪلون [بنيادي دروازن جي فهرست]) هن معيار سان تضاد ۾ نه سمجهيو ويندو گهرجي. پيچيده علامتن ٺاهڻ لاءِ انهن ٻين علامتن جو استعمال، مثال طور، ايمبيڊڊ علامتن جي طور تي استعمال، جي حوصلا افزائي ڪئي وئي آهي." اهو سمجهوتو لاڳاپيل IEEE ۽ IEC ورڪنگ گروپن جي وچ ۾، IEEE ۽ IEC معيارن کي هڪ ٻئي سان باهمي تعميل ۾ هجڻ جي اجازت ڏيڻ لاءِ ٿيو. 1980ع جي ڏهاڪي ۾، اسڪيميٽڪ سرڪٽ بورڊ ۽ ڪسٽم IC ٻنهي کي ڊزائين ڪرڻ جو غالب طريقو هو، جيڪو "گيٽ ايري" (Gate Array) جي نالي سان سڃاتو وڃي ٿو. اڄڪلهه ڪسٽم آئي سي ۽ فيلڊ-پروگراميبل گيٽ ايري عام طور تي هارڊويئر وضاحتي ٻولين (HDL)، جهڙوڪ ويريلاگ يا وي ايڇ ڊي ايل، سان ٺهيل آهن. {| class="wikitable" style="text-align:center;" |- ! Type !! Distinctive shape<br />(IEEE Std 91/91a-1991) !! Rectangular shape<br />(IEEE Std 91/91a-1991)<br />(IEC 60617-12:1997) !! [[Boolean algebra]] between A and B !! [[Truth table]] |- ! colspan="5" | Single-input gates |- | '''[[Buffer gate|Buffer]]''' | [[File:Buffer ANSI Labelled.svg|Buffer symbol|class=skin-invert-image]] | [[File:Buffer IEC Labelled.svg|Buffer symbol|class=skin-invert-image]] | <math>{A}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |'''Input''' || '''Output''' |- style="background:#def;" | A || Q |- | {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} |} |- | '''[[NOT gate|NOT]]'''<br />(inverter) | [[File:NOT ANSI Labelled.svg|NOT symbol|class=skin-invert-image]] | [[File:NOT IEC Labelled.svg|NOT symbol|class=skin-invert-image]] | <math>\overline{A}</math> or <math>\neg A</math> | {| class="wikitable" style="float:right;" |- style="background:#def; text-align:center;" | '''Input''' || '''Output''' |- style="background:#def; text-align:center;" | A || Q |- | {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'' and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or low voltage level = 1, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful. |- ! colspan="5" |[[Logical conjunction|Conjunction]] and [[disjunction]] |- | '''[[AND gate|AND]]''' | [[File:AND ANSI Labelled.svg|AND symbol|class=skin-invert-image]] | [[File:AND IEC Labelled.svg|AND symbol|class=skin-invert-image]] | <math>A \cdot B</math> or <math>A \land B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |-" | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[OR gate|OR]]''' | [[File:OR ANSI Labelled.svg|OR symbol|class=skin-invert-image]] | [[File:OR IEC Labelled.svg|OR symbol|class=skin-invert-image]] | <math>A+B</math> or <math>A \lor B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Alternative denial]] and [[joint denial]] |- | '''[[NAND gate|NAND]]''' | [[File:NAND ANSI Labelled.svg|NAND symbol|class=skin-invert-image]] | [[File:NAND IEC Labelled.svg|NAND symbol|class=skin-invert-image]] | <math>\overline{A \cdot B}</math> or <math>A \uparrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | '''[[NOR gate|NOR]]''' | [[File:NOR ANSI Labelled.svg|NOR symbol|class=skin-invert-image]] | [[File:NOR IEC Labelled.svg|NOR symbol|class=skin-invert-image]] | <math>\overline{A + B}</math> or <math>A \downarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- ! colspan="5" |[[Exclusive or]] and [[biconditional]] |- | '''[[XOR gate|XOR]]''' | [[File:XOR ANSI Labelled.svg|XOR symbol|class=skin-invert-image]] | [[File:XOR IEC Labelled.svg|XOR symbol|class=skin-invert-image]] | <math>A \oplus B</math> or <math>A \veebar B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |The output of a two input exclusive-OR is true only when the two input values are ''different'', and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol. |- | '''[[XNOR]]''' | [[File:XNOR ANSI Labelled.svg|XNOR symbol|class=skin-invert-image]] | [[File:XNOR IEC Labelled.svg|XNOR symbol|class=skin-invert-image]] | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- ! colspan="5" |[[Material conditional|Implication]] and [[Material nonimplication|Nonimplication]] |- | '''[[IMPLY]]'''<ref>{{cite book|title=Mathematics for Computer Science|date=2015|page=41|url=https://people.csail.mit.edu/meyer/mcs.pdf}}</ref> | [[File:IMPLY ANSI.svg|IMPLY symbol|class=skin-invert-image]] | | <math>\overline{A}+B</math> or <math>A \rightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | {{no2|0}} || {{yes2|1}} || {{yes2|1}} |- | {{yes2|1}} || {{no2|0}} || {{no2|0}} |- | {{yes2|1}} || {{yes2|1}} || {{yes2|1}} |} |- | '''[[NIMPLY]]''' | [[File:NIMPLY ANSI.svg|NIMPLY symbol|class=skin-invert-image]] | | <math>A \cdot \overline{B}</math> or <math>A \nrightarrow B</math> | {| class="wikitable" style="float:right;text-align:center;" |- style="background:#def;" |colspan=2|'''Input''' || '''Output''' |- style="background:#def;" | A || B || Q |- | {{no2|0}} || {{no2|0}} || {{no2|0}} |- | {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | {{yes2|1}} || {{no2|0}} || {{yes2|1}} |- | {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} |- | colspan="5" style="text-align:left;" |IMPLY and NIMPLY are not [[commutative]], meaning that changing the order of the operands may change the result. For instance, <math>A \rightarrow \overline{B}</math> is false, but <math>\overline{A} \rightarrow B</math> is true; likewise, <math>A \nrightarrow \overline{B}</math> is true, but <math>\overline{A} \nrightarrow B</math> is false. |} ==ڊي مورگن جي برابر علامتون== By use of [[De Morgan's laws]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated. A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor. De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons. ==ٽرٿ ٽيبلز== Output comparison of various logic gates: {| class="wikitable" style="text-align:center; |+ 1-input logic gates |- style="background:#def;" | colspan=1 | '''Input''' || colspan=2 | '''Output''' |- style="background:#def;" | A || Buffer || Inverter |- | 0 || {{no2|0}} || {{yes2|1}} |- | 1 || {{yes2|1}} || {{no2|0}} |} {| class="wikitable" style="text-align:center;" |+ 2-input logic gates |- style="background:#def;" | colspan=2 | '''Input''' || colspan=8 | '''Output''' |- style="background:#def;" | A || B || AND || NAND || OR || NOR || XOR || XNOR || IMPLY || NIMPLY |- | 0 || 0 || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |- | 0 || 1 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} |- | 1 || 0 || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} |- | 1 || 1 || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} |} ==يونيورسل لاجڪ گيٽس== {{further|topic=the theoretical basis|Functional completeness}} [[Charles Sanders Peirce]] (during 1880–1881) showed that [[NOR logic|NOR gates alone]] (or alternatively [[NAND logic|NAND gates alone]]) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–1881), "A Boolian Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218–221, Google [https://archive.org/details/writingsofcharle0004peir/page/218]. See {{cite book |author-last=Roberts |author-first=Don D. |title=The Existential Graphs of Charles S. Peirce |date=2009 |publisher=[[De Gruyter]] |isbn=978-3-11022622-5 |page=131 |chapter=7.12 The Graphical Analysis of Propositions |chapter-url=https://books.google.com/books?id=Q4K30wCAf-gC&pg=PA113}}</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called ''[[Sheffer stroke]]''; the [[logical NOR]] is sometimes called ''[[Peirce's arrow]]''.<ref name="BüningLettmann1999">{{cite book |author-first1=Hans Kleine |author-last1=Büning |author-first2=Theodor |author-last2=Lettmann |title=Propositional logic: deduction and algorithms |url=https://books.google.com/books?id=3oJE9yczr3EC&pg=PA2 |date=1999 |publisher=[[Cambridge University Press]] |isbn=978-0-521-63017-7 |page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book |author-first=John |author-last=Bird |title=Engineering mathematics |url=https://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532 |date=2007 |publisher=[[Newnes (publisher)|Newnes]] |isbn=978-0-7506-8555-9 |page=532}}</ref> {| class="wikitable skin-invert-image" |+ Logic gate constructions from only NAND or only NOR ! scope="col" | Type ! scope="col" | NAND construction ! scope="col" | NOR construction |- ! scope="row" | NOT |[[File:NOT from NAND.svg|alt=Circuit diagram: NAND(A, A)]] |[[File:NOT from NOR.svg|alt=Circuit diagram: NOR(A, A)]] |- ! scope="row" | AND |[[File:AND from NAND.svg|alt=Circuit diagram: NAND(NAND(A, B), NAND(A, B))]] |[[File:AND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, A), NOR(B, B))]] |- ! scope="row" | NAND |[[File:NAND ANSI Labelled.svg|alt=Circuit diagram: NAND(A, B)]] |[[File:NAND from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | OR |[[File:OR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, A), NAND(B, B))]] |[[File:OR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, B), NOR(A, B))]] |- ! scope="row" | NOR |[[File:NOR from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)))]] |[[File:NOR ANSI Labelled.svg|alt=Circuit diagram: NOR(A, B)]] |- ! scope="row" | XOR |[[File:XOR from NAND.svg|alt=Circuit diagram: NAND(NAND(A, NAND(A, B)), NAND(NAND(A, B), B))]] |[[File:XOR from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), NOR(B, B)), NOR(A, B))]] |- ! scope="row" | XNOR |[[File:XNOR from NAND 2.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(B, B)), NAND(A, B))]] |[[File:XNOR from NOR.svg|alt=Circuit diagram: NOR(NOR(A, NOR(A, B)), NOR(NOR(A, B), B))]] |- ! scpoe="row" | IMPLY |[[File:IMPLY from NAND.svg|alt=Circuit diagram: NAND(NAND(NAND(A, A), NAND(A, A)), NAND(B, B)]] |[[File:IMPLY from NOR.svg|alt=Circuit diagram: NOR(NOR(NOR(A, A), B), NOR(NOR(A, A), B))]] |- ! scope="row" | NIMPLY |<!--File is missing.--> |<!--File is missing.--> |} ==ڊيٽا اسٽوريج ۽ ترتيب وار منطق== [[File:R-S mk2.gif|thumb|Animation of how an SR [[NOR gate]] latch works]] Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. Latching circuitry is used in [[static random-access memory]]. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flops]]". Formally, a flip-flop is called a [[bistable circuit]], because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, used to store a multiple-bit value, is known as a [[hardware register|register]]. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s), i.e. by the ''sequence'' of input states. In contrast, the output from [[combinational logic]] is purely a combination of its present inputs, unaffected by the previous input and output states. These logic circuits are used in computer [[computer memory|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the application. ==صنعتي تياري== {{See also|Unconventional computing|Semiconductor device fabrication}} ===اليڪٽرانڪ گيٽ=== A [[functionally complete]] logic system may be composed of [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s. Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[Gain (electronics)|gain]] [[voltage]] [[amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate. [[File:TexasInstruments 7400 chip, view and element placement.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]] For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor–transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]], the [[CMOS]] [[4000 series]] by [[RCA Corporation|RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature of [[programmable logic device]]s such as [[FPGA]]s has reduced the "hard" property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed. An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered. The output of one gate can only drive a finite number of inputs to other gates, a number called the "[[fan-out]] limit". Also, there is always a delay, called the "[[propagation delay]]", from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed [[synchronous circuit]]s. Additional delay can be caused when many inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide. ====Logic families==== {{Main| Logic family}} There are several [[logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor–diode logic), [[resistor–transistor logic|RTL]] (resistor–transistor logic), [[DTL]] (diode–transistor logic), [[transistor–transistor logic|TTL]] (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors. The simplest family of logic gates uses [[bipolar transistors]], and is called [[resistor–transistor logic]] (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in early [[integrated circuit]]s. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting in [[diode–transistor logic]] (DTL). [[Transistor–transistor logic]] (TTL) then supplanted DTL. [[File:CMOS inverter.svg|thumb|125px|[[CMOS]] diagram of a [[NOT gate]], also known as an inverter. [[MOSFET]]s are the most common way to make logic gates.]] As integrated circuits became more complex, bipolar transistors were replaced with smaller [[field-effect transistor]]s ([[MOSFET]]s); see [[PMOS logic|PMOS]] and [[NMOS logic|NMOS]]. To reduce power consumption still further, most contemporary chip implementations of digital systems now use [[CMOS]] logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation. Other types of logic gates include, but are not limited to:<ref>{{cite news |author-last=Rowe |author-first=Jim |title=Circuit Logic – Why and How |agency=Electronics Australia |issue=December 1966}}</ref> {| class="wikitable" |+ ! Logic family !! Abbreviation !! Description |- | [[Diode logic]]|| DL || |- | Tunnel diode logic || TDL || Exactly the same as diode logic but can perform at a higher speed.{{failed verification|reason=Tunnel diodes have gain and state|date=December 2017}} |- | Neon logic || NL || Uses neon bulbs or 3-element neon trigger tubes to perform logic. |- | Core diode logic || CDL || Performed by semiconductor diodes and small ferrite toroidal cores for moderate speed and moderate power level. |- | 4Layer Device Logic || 4LDL || Uses thyristors and SCRs to perform logic operations where high current and or high voltages are required. |- | [[Direct-coupled transistor logic]] || DCTL || Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic. |- | [[Metal–oxide–semiconductor]] logic || MOS || Uses [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includes [[PMOS logic]], [[NMOS logic]], [[complementary MOS]] (CMOS), and [[BiCMOS]] (bipolar CMOS). |- | [[Current-mode logic]] || CML || Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels. |- | [[Quantum dot cellular automaton|Quantum-dot cellular automata]] | QCA | Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds. |- | Ferroelectric FET || FeFET || FeFET transistors can retain their state to speed recovery in case of a power loss.<ref>{{cite web | url=https://semiengineering.com/tapping-into-non-volatile-logic/ | title=Tapping into Non-Volatile Logic | date=21 April 2021 }}</ref> |} ====Three-state logic gates==== [[File:Tristate buffer.svg|thumb|320px|right|A three-state buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]] {{Main|Three-state logic}} A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|buses]] of the [[CPU]] to allow multiple chips to send data. A group of three-state outputs driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards. In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit. === Non-electronic logic gates === Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.<ref>{{cite web |author-link=Ralph C. Merkle |author-first=Ralph C. |author-last=Merkle |title=Two Types of Mechanical Reversible Logic |date=1993 |publisher=[[Xerox PARC]] |url=http://www.zyvex.com/nanotech/mechano.html}}</ref> Various types of fundamental logic gates have been constructed using molecules ([[molecular logic gate]]s), which are based on chemical inputs and spectroscopic outputs.<ref>{{Cite journal |last1=Erbas-Cakmak |first1=Sundus |last2=Kolemen |first2=Safacan |last3=Sedgwick |first3=Adam C. |last4=Gunnlaugsson |first4=Thorfinnur |last5=James |first5=Tony D. |last6=Yoon |first6=Juyoung |last7=Akkaya |first7=Engin U. |date=2018 |title=Molecular logic gates: the past, present and future |url=http://xlink.rsc.org/?DOI=C7CS00491E |journal=Chemical Society Reviews |language=en |volume=47 |issue=7 |pages=2228–2248 |doi=10.1039/C7CS00491E |pmid=29493684 |issn=0306-0012|hdl=11693/50034 |hdl-access=free }}</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>{{cite journal |author-first1=Milan N. |author-last1=Stojanovic |author-first2=Tiffany E. |author-last2=Mitchell |author-first3=Darko |author-last3=Stefanovic |title=Deoxyribozyme-Based Logic Gates |journal=[[Journal of the American Chemical Society]] |volume=124 |issue=14 |pages=3555–3561 |date=2002 |doi=10.1021/ja016756v |pmid=11929243 |bibcode=2002JAChS.124.3555S |url=https://pubs.acs.org/doi/abs/10.1021/ja016756v|url-access=subscription }}</ref> and used to create a computer called MAYA (see [[MAYA-II]]). Logic gates can be made from [[quantum mechanical]] effects, see [[quantum logic gate]]. [[Photonic logic]] gates use [[nonlinear optical]] effects. In principle any method that leads to a gate that is [[functionally complete]] (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates). ==پڻ ڏسو== * [[ڪمپيوٽنگ]] * بولين الجبرا * ڊجيٽل سرڪٽ * انٽيگريٽڊ سرڪٽ * پروسيسر * ٽرٿ ٽيبل * [[And-inverter graph]] * [[Boolean algebra topics]] * [[Boolean function]] * [[Depletion-load NMOS logic]] * [[Electronic symbol]] * [[Espresso heuristic logic minimizer]] * [[Emitter-coupled logic]] * [[Fan-out]] * [[Field-programmable gate array]] (FPGA) * [[Flip-flop (electronics)]] * [[Functional completeness]] * [[Integrated injection logic]] * [[Karnaugh map]] * [[Combinational logic]] * [[List of 4000 series integrated circuits]] * [[List of 7400 series integrated circuits]] * [[Logic family]] * [[Logic level]] * [[Logical graph]] * [[Logic redundancy]] * [[Magnetic logic]] * [[NMOS logic]] * [[Parametron]] * [[Processor design]] * [[Programmable logic controller]] (PLC) * [[Programmable logic device]] (PLD) * [[Propositional calculus]] * [[Race hazard]] * [[Reversible computing]] * [[Superconducting computing]] * [[Unconventional computing]] ==حوالا== {{حوالا}} ==وڌيڪ مطالعي لاء== * {{cite book |author-last=Bostock |author-first=Geoff |title=Programmable logic devices: technology and applications |url=https://books.google.com/books?id=XEFTAAAAMAAJ |date=1988 |publisher=[[McGraw-Hill]] |isbn=978-0-07-006611-3}} * {{cite book |author-last1=Brown |author-first1=Stephen D. |author-last2=Francis |author-first2=Robert J. |author-last3=Rose |author-first3=Jonathan |author-first4=Zvonko G. |author-last4=Vranesic |title=Field Programmable Gate Arrays|url=https://books.google.com/books?id=8s4M-qYOWZIC |date=1992 |publisher=[[Kluwer Academic]] |isbn=978-0-7923-9248-4}} ==ٻاهريان ڳنڍڻا== * {{Commons category-inline|لاجڪ گيٽ}} {{Authority control}} [[زمرو:لاجڪ گيٽ]] [[زمرو:لاجڪ گيٽس]] [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:ڪمپيوٽر انجنيئرنگ]] [[زمرو:ڪمپيوٽر سسٽم]] g8bz92ch8q58dpieo4zun7tfw8omuag 14 95016 371834 2026-04-16T20:34:17Z Ibne maryam 17680 نئون صفحو: [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] 371834 wikitext text/x-wiki [[زمرو:الگورٿم]] [[زمرو:بولين الجبرا]] 2dawq9mqi0mas569ui7xfe0z12sehe3 14 95017 371840 2026-04-16T20:49:57Z Ibne maryam 17680 نئون صفحو: [[زمرو:ڪمپيوٽر]] [[زمرو:اليڪٽرانڪ جزا]] [[زمرو:بنيادي ڪمپيوٽر جزا]] 371840 wikitext text/x-wiki [[زمرو:ڪمپيوٽر]] [[زمرو:اليڪٽرانڪ جزا]] [[زمرو:بنيادي ڪمپيوٽر جزا]] rp64mlu0mj19phlrs242vci8k87a5j5 371842 371840 2026-04-16T20:51:05Z Ibne maryam 17680 removed [[Category:ڪمپيوٽر]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371842 wikitext text/x-wiki [[زمرو:اليڪٽرانڪ جزا]] [[زمرو:بنيادي ڪمپيوٽر جزا]] hhu993u3qg4wl5g21u6x79l5by45vd0 14 95018 371841 2026-04-16T20:50:24Z Ibne maryam 17680 نئون صفحو: [[زمرو:ڪمپيوٽر هارڊويئر]] 371841 wikitext text/x-wiki [[زمرو:ڪمپيوٽر هارڊويئر]] 3qe6o1sriva0w39x0kg95060he48eoa 14 95019 371843 2026-04-16T20:51:50Z Ibne maryam 17680 نئون صفحو: [[زمرو:ٽيڪنالاجي]] 371843 wikitext text/x-wiki [[زمرو:ٽيڪنالاجي]] aw8hb6vrytwzi5ijfel43vvacev3px2 371848 371843 2026-04-16T21:04:07Z Ibne maryam 17680 371848 wikitext text/x-wiki [[زمرو:ٽيڪنالاجي]] [[زمرو:اليڪٽرانڪس]] htqz444otnyzcta5xmpkd3tbfq9a8ws 14 95020 371844 2026-04-16T20:53:14Z Ibne maryam 17680 نئون صفحو: [[زمرو:ڪمپيوٽر سسٽم]] [[زمرو:ڊجيٽل اليڪٽرانڪس]] 371844 wikitext text/x-wiki [[زمرو:ڪمپيوٽر سسٽم]] [[زمرو:ڊجيٽل اليڪٽرانڪس]] suw41n5t1zy1teiwnw15mqcskjon1db 14 95021 371846 2026-04-16T20:59:21Z Ibne maryam 17680 نئون صفحو: [[زمرو:اليڪٽرانڪس]] [[زمرو:انجنيئرنگ جا شعبا]] 371846 wikitext text/x-wiki [[زمرو:اليڪٽرانڪس]] [[زمرو:انجنيئرنگ جا شعبا]] mo1w6c1jtcwhwwvefof2d09zztqo07t 14 95022 371847 2026-04-16T21:00:13Z Ibne maryam 17680 نئون صفحو: [[زمرو:ٽيڪنالاجي]] [[زمرو:طبعيات جو شاخون]] 371847 wikitext text/x-wiki [[زمرو:ٽيڪنالاجي]] [[زمرو:طبعيات جو شاخون]] c7a2iv8slbxcifzzylrfmv6u51xoiyh 14 95023 371849 2026-04-16T21:04:51Z Ibne maryam 17680 نئون صفحو: [[زمرو:اليڪٽرانڪس]] 371849 wikitext text/x-wiki [[زمرو:اليڪٽرانڪس]] gijatin5herapdd8ztgpw69rqeyro6v 0 95024 371853 2026-04-17T06:34:12Z Ibne maryam 17680 نئون صفحو: '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرام... 371853 wikitext text/x-wiki '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] 2fmcj20za3d49usznahpu7jq5g58hjr 371854 371853 2026-04-17T06:37:15Z Ibne maryam 17680 /* ٻاهريان ڳنڍڻا */ 371854 wikitext text/x-wiki '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] 31jvrt6uciiit0lczeo6wa14iezjk1a 371855 371854 2026-04-17T06:39:56Z Ibne maryam 17680 /* ٻاهريان ڳنڍڻا */ 371855 wikitext text/x-wiki '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرنگ]] 20dzmuyrhvgltpdusi4qux377ddouzk 371856 371855 2026-04-17T06:41:04Z Ibne maryam 17680 removed [[Category:سافٽ ويئر انجنيئرنگ]]; added [[Category:سافٽ ويئر انجنيئرڱ]] [[وڪيپيڊيا:ھاٽ ڪيٽ|ھاٽ ڪيت]] جي مدد سان 371856 wikitext text/x-wiki '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] d9ttupj1o294f1y2t5s88totkget789 371866 371856 2026-04-17T10:56:48Z Ibne maryam 17680 371866 wikitext text/x-wiki [[File:Ada lovelace.jpg|thumb|[[Ada Lovelace]], whose notes were added to the end of [[Luigi Menabrea]]'s paper included the first [[algorithm]] designed for processing by [[Charles Babbage]]'s [[Analytical Engine]]. She is often recognized as history's first computer programmer.]] '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] 9j9xk26x6lhvsap7gtcide3wvasn06p 371867 371866 2026-04-17T11:08:09Z Ibne maryam 17680 371867 wikitext text/x-wiki [[File:Ada lovelace.jpg|thumb|[[Ada Lovelace]], whose notes were added to the end of [[Luigi Menabrea]]'s paper included the first [[algorithm]] designed for processing by [[Charles Babbage]]'s [[Analytical Engine]]. She is often recognized as history's first computer programmer.]] '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==جديد پروگرامنگ== ==پروگرامنگ ٻوليون== ==پروگرامنگ سکڻ== ==پروگرامر== مکيه مضمون: پروگرامر ۽ سافٽ ويئر انجنيئر ڪمپيوٽر پروگرامر اهي آهن جيڪي ڪمپيوٽر سافٽ ويئر لکن ٿا. انهن جي ڪمن ۾ عام طور تي شامل آهن: * پروٽوٽائپنگ * ڪوڊنگ * ڊيبگنگ * ڊاڪيومينٽيشن * انٽيگريشن * ساڙ سنڀال * ضرورتن جو تجزيو * سافٽ ويئر آرڪيٽيڪچر *سافٽ ويئر ٽيسٽنگ وضاحت: جيتوڻيڪ پروگرامنگ کي ميڊيا ۾ ڪجهه حد تائين رياضياتي موضوع طور پيش ڪيو ويو آهي. ڪجهه تحقيق ڏيکاري ٿي ته سٺا پروگرامر قدرتي انساني ٻولين ۾ مضبوط صلاحيتون رکن ٿا ۽ ڪوڊ سکڻ هڪ غير ملڪي ٻولي سکڻ جي برابر آهي. ==پڻ ڏسو== * ڪمپيوٽر پورٽل * ڪمپيوٽر پروگرامنگ جو خاڪو. * ڪمپيوٽر نيٽ ورڪنگ * پروگرامنگ لاءِ مفت ۽ اوپن سورس سافٽ ويئر پيڪيجز جي فهرست * پروگرامنگ سافٽ ويئر ڊولپمينٽ ٽولز جي فهرست * سسٽم پروگرامنگ * وڪي بڪ ڪمپيوٽر پروگرامنگ وسيلا ==حوالا== ==وڌيڪ پڙهڻ== ==ٻاهرين لنڪس== ==حوالا== {{حوالا}} ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] pfztwb6buw482uvmjmrnnsp9eoprv3i 371868 371867 2026-04-17T11:08:52Z Ibne maryam 17680 371868 wikitext text/x-wiki [[File:Ada lovelace.jpg|thumb|[[Ada Lovelace]], whose notes were added to the end of [[Luigi Menabrea]]'s paper included the first [[algorithm]] designed for processing by [[Charles Babbage]]'s [[Analytical Engine]]. She is often recognized as history's first computer programmer.]] '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==جديد پروگرامنگ== ==پروگرامنگ ٻوليون== ==پروگرامنگ سکڻ== ==پروگرامر== مکيه مضمون: پروگرامر ۽ سافٽ ويئر انجنيئر ڪمپيوٽر پروگرامر اهي آهن جيڪي ڪمپيوٽر سافٽ ويئر لکن ٿا. انهن جي ڪمن ۾ عام طور تي شامل آهن: * پروٽوٽائپنگ * ڪوڊنگ * ڊيبگنگ * ڊاڪيومينٽيشن * انٽيگريشن * ساڙ سنڀال * ضرورتن جو تجزيو * سافٽ ويئر آرڪيٽيڪچر *سافٽ ويئر ٽيسٽنگ وضاحت: جيتوڻيڪ پروگرامنگ کي ميڊيا ۾ ڪجهه حد تائين رياضياتي موضوع طور پيش ڪيو ويو آهي. ڪجهه تحقيق ڏيکاري ٿي ته سٺا پروگرامر قدرتي انساني ٻولين ۾ مضبوط صلاحيتون رکن ٿا ۽ ڪوڊ سکڻ هڪ غير ملڪي ٻولي سکڻ جي برابر آهي. ==پڻ ڏسو== * ڪمپيوٽر پورٽل * ڪمپيوٽر پروگرامنگ جو خاڪو. * ڪمپيوٽر نيٽ ورڪنگ * پروگرامنگ لاءِ مفت ۽ اوپن سورس سافٽ ويئر پيڪيجز جي فهرست * پروگرامنگ سافٽ ويئر ڊولپمينٽ ٽولز جي فهرست * سسٽم پروگرامنگ * وڪي بڪ ڪمپيوٽر پروگرامنگ وسيلا ==حوالا== ==وڌيڪ پڙهڻ== ==ٻاهرين لنڪس== ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] flxfkt09ymya2b1d44bv6zmvkc0fw6t 371869 371868 2026-04-17T11:09:15Z Ibne maryam 17680 /* حوالا */ 371869 wikitext text/x-wiki [[File:Ada lovelace.jpg|thumb|[[Ada Lovelace]], whose notes were added to the end of [[Luigi Menabrea]]'s paper included the first [[algorithm]] designed for processing by [[Charles Babbage]]'s [[Analytical Engine]]. She is often recognized as history's first computer programmer.]] '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==جديد پروگرامنگ== ==پروگرامنگ ٻوليون== ==پروگرامنگ سکڻ== ==پروگرامر== مکيه مضمون: پروگرامر ۽ سافٽ ويئر انجنيئر ڪمپيوٽر پروگرامر اهي آهن جيڪي ڪمپيوٽر سافٽ ويئر لکن ٿا. انهن جي ڪمن ۾ عام طور تي شامل آهن: * پروٽوٽائپنگ * ڪوڊنگ * ڊيبگنگ * ڊاڪيومينٽيشن * انٽيگريشن * ساڙ سنڀال * ضرورتن جو تجزيو * سافٽ ويئر آرڪيٽيڪچر *سافٽ ويئر ٽيسٽنگ وضاحت: جيتوڻيڪ پروگرامنگ کي ميڊيا ۾ ڪجهه حد تائين رياضياتي موضوع طور پيش ڪيو ويو آهي. ڪجهه تحقيق ڏيکاري ٿي ته سٺا پروگرامر قدرتي انساني ٻولين ۾ مضبوط صلاحيتون رکن ٿا ۽ ڪوڊ سکڻ هڪ غير ملڪي ٻولي سکڻ جي برابر آهي. ==پڻ ڏسو== * ڪمپيوٽر پورٽل * ڪمپيوٽر پروگرامنگ جو خاڪو. * ڪمپيوٽر نيٽ ورڪنگ * پروگرامنگ لاءِ مفت ۽ اوپن سورس سافٽ ويئر پيڪيجز جي فهرست * پروگرامنگ سافٽ ويئر ڊولپمينٽ ٽولز جي فهرست * سسٽم پروگرامنگ * وڪي بڪ ڪمپيوٽر پروگرامنگ وسيلا ==حوالا== {{حوالا}} ==وڌيڪ پڙهڻ== ==ٻاهرين لنڪس== ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] 43j124izd3z7v7146tt02xzclmwrknd 371870 371869 2026-04-17T11:09:30Z Ibne maryam 17680 371870 wikitext text/x-wiki [[File:Ada lovelace.jpg|thumb|[[Ada Lovelace]], whose notes were added to the end of [[Luigi Menabrea]]'s paper included the first [[algorithm]] designed for processing by [[Charles Babbage]]'s [[Analytical Engine]]. She is often recognized as history's first computer programmer.]] '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==جديد پروگرامنگ== ==پروگرامنگ ٻوليون== ==پروگرامنگ سکڻ== ==پروگرامر== مکيه مضمون: پروگرامر ۽ سافٽ ويئر انجنيئر ڪمپيوٽر پروگرامر اهي آهن جيڪي ڪمپيوٽر سافٽ ويئر لکن ٿا. انهن جي ڪمن ۾ عام طور تي شامل آهن: * پروٽوٽائپنگ * ڪوڊنگ * ڊيبگنگ * ڊاڪيومينٽيشن * انٽيگريشن * ساڙ سنڀال * ضرورتن جو تجزيو * سافٽ ويئر آرڪيٽيڪچر *سافٽ ويئر ٽيسٽنگ وضاحت: جيتوڻيڪ پروگرامنگ کي ميڊيا ۾ ڪجهه حد تائين رياضياتي موضوع طور پيش ڪيو ويو آهي. ڪجهه تحقيق ڏيکاري ٿي ته سٺا پروگرامر قدرتي انساني ٻولين ۾ مضبوط صلاحيتون رکن ٿا ۽ ڪوڊ سکڻ هڪ غير ملڪي ٻولي سکڻ جي برابر آهي. ==پڻ ڏسو== * ڪمپيوٽر پورٽل * ڪمپيوٽر پروگرامنگ جو خاڪو. * ڪمپيوٽر نيٽ ورڪنگ * پروگرامنگ لاءِ مفت ۽ اوپن سورس سافٽ ويئر پيڪيجز جي فهرست * پروگرامنگ سافٽ ويئر ڊولپمينٽ ٽولز جي فهرست * سسٽم پروگرامنگ * وڪي بڪ ڪمپيوٽر پروگرامنگ وسيلا ==حوالا== {{حوالا}} ==وڌيڪ پڙهڻ== ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] 62exffteoh5ewwyqm73xlbimhts6aci 371871 371870 2026-04-17T11:11:13Z Ibne maryam 17680 /* پڻ ڏسو */ 371871 wikitext text/x-wiki [[File:Ada lovelace.jpg|thumb|[[Ada Lovelace]], whose notes were added to the end of [[Luigi Menabrea]]'s paper included the first [[algorithm]] designed for processing by [[Charles Babbage]]'s [[Analytical Engine]]. She is often recognized as history's first computer programmer.]] '''ڪمپيوٽر پروگرامنگ''' يا ڪوڊنگ هدايتن جي تسلسل، جنهن کي پروگرام سڏيو ويندو آهي، جو مجموعو آهي جنهن تي ڪمپيوٽر ڪم ڪرڻ لاءِ عمل ڪري سگهن ٿا. ان ۾ الگورتھم ڊيزائن ڪرڻ ۽ لاڳو ڪرڻ، طريقيڪار جي قدم بہ قدم وضاحتون شامل آهن. هڪ يا وڌيڪ پروگرامنگ ٻولين ۾ ڪوڊ لکڻ سان. پروگرامر عام طور تي اعليٰ سطحي پروگرامنگ ٻوليون استعمال ڪندا آهن، جيڪي مشين ڪوڊ جي ڀيٽ ۾ انسانن لاءِ وڌيڪ آساني سان سمجھڻ ۾ اچن ٿيون، جيڪي سڌو سنئون مرڪزي پروسيسنگ يونٽ پاران عمل ۾ آنديون وينديون آهن. ماهر پروگرامنگ کي عام طور تي، ايپليڪيشن ڊومين جي ڄاڻ سميت ڪيترن ئي مختلف مضمونن ۾ مهارت جي ضرورت هوندي آهي، جئين ته پروگرامنگ ٻولين ۽ عام ڪوڊ لائبريرين جي تفصيل، خاص الگورٿم ۽ رسمي منطق. پروگرامنگ سان گڏ ۽ لاڳاپيل معاون ڪمن ۾ ضرورتن جو تجزيو ڪرڻ، ٽيسٽنگ، ڊيبگنگ (مسائل جي جاچ ۽ حل ڪرڻ)، بلڊ سسٽم جو نفاذ ۽ نڪتل نمونن جو انتظام، جهڙوڪ پروگرامن جو مشين ڪوڊ، شامل آهن. جڏهن ته انهن کي ڪڏهن ڪڏهن پروگرامنگ سمجهيو ويندو آهي، اڪثر ڪري سافٽ ويئر ڊولپمينٽ جو اصطلاح هن وڏي مجموعي عمل لاءِ استعمال ڪيو ويندو آهي - اصطلاحن سان پروگرامنگ، عملدرآمد ۽ ڪوڊنگ ڪوڊ جي لکڻ ۽ ايڊيٽنگ لاءِ مخصوص آهن. ڪڏهن ڪڏهن سافٽ ويئر ڊولپمينٽ کي سافٽ ويئر انجنيئرنگ طور سڃاتو وڃي ٿو، خاص طور تي جڏهن اهو رسمي طريقا استعمال ڪري ٿو يا انجنيئرنگ ڊيزائن جي عمل جي پيروي ڪري ٿو. ==تاريخ== ==جديد پروگرامنگ== ==پروگرامنگ ٻوليون== ==پروگرامنگ سکڻ== ==پروگرامر== مکيه مضمون: پروگرامر ۽ سافٽ ويئر انجنيئر ڪمپيوٽر پروگرامر اهي آهن جيڪي ڪمپيوٽر سافٽ ويئر لکن ٿا. انهن جي ڪمن ۾ عام طور تي شامل آهن: * پروٽوٽائپنگ * ڪوڊنگ * ڊيبگنگ * ڊاڪيومينٽيشن * انٽيگريشن * ساڙ سنڀال * ضرورتن جو تجزيو * سافٽ ويئر آرڪيٽيڪچر *سافٽ ويئر ٽيسٽنگ وضاحت: جيتوڻيڪ پروگرامنگ کي ميڊيا ۾ ڪجهه حد تائين رياضياتي موضوع طور پيش ڪيو ويو آهي. ڪجهه تحقيق ڏيکاري ٿي ته سٺا پروگرامر قدرتي انساني ٻولين ۾ مضبوط صلاحيتون رکن ٿا ۽ ڪوڊ سکڻ هڪ غير ملڪي ٻولي سکڻ جي برابر آهي. ==پڻ ڏسو== {{Portal|Computer|Computer Programming}} * ڪمپيوٽر پروگرامنگ جو خاڪو * ڪمپيوٽر نيٽ ورڪنگ * پروگرامنگ لاءِ مفت ۽ اوپن سورس سافٽ ويئر پيڪيجز جي فهرست * پروگرامنگ سافٽ ويئر ڊولپمينٽ ٽولز جي فهرست * سسٽم پروگرامنگ * وڪي بڪ ڪمپيوٽر پروگرامنگ وسيلا ==حوالا== {{حوالا}} ==وڌيڪ پڙهڻ== ==ٻاهريان ڳنڍڻا== {{Library resources box|onlinebooks=yes}} {{Wikibooks|Computer Programming}} {{Wikibooks|Windows Programming}} {{Wikiversity|Computer Programming}} *{{Commons category-inline|Computer programming}} *{{Wikiquote-inline|Programming}} <!--Please see this URL before adding external links here: http://meta.wikimedia.org/wiki/When_should_I_link_externally--> {{Authority control}} {{DEFAULTSORT:Computer Programming}} [[زمرو:ڪمپيوٽر پروگرامنگ]] [[زمرو:ڪمپيوٽر|پروگرامنگ]] [[زمرو:ڪمپيوٽر سائنس]] [[زمرو:سافٽ ويئر انجنيئرڱ]] iocqlthjgjs14nwk6qftjhsjggphcwq